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21.发明授权Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare 有权方法和和寻址单元编码器，用于CAM比较的增强比较和搜索时序公开(公告)号：US07035127B1
公开(公告)日：2006-04-25
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译： 提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。 应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。 然后将编码的真实和补码位信号应用于关键路径动态比较电路。 编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。
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22.发明授权Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage 失效实现对多米诺骨牌SRAM的局部评估，具有增强的SRAM单元稳定性，同时最小化区域使用率公开(公告)号：US07724586B2
公开(公告)日：2010-05-25
申请号：US12195151
申请日：2008-08-20
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.
摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 实现相关SRAM单元组的读和写操作的SRAM本地评估电路包括真和补补位线，真和补写写数据传播输入，预充电信号和预充电写信号。 相应的预充电装置连接在电压源VDD与真位线和补码位线之间。 第一传递门装置连接在补码位线和真实写入数据传播输入端之间。 第二个通路装置连接在真位线和补码写入数据传播输入之间。 在读取操作期间，预充电写信号禁用通路器件。 在写入操作期间，预充电写入信号使能通路装置。
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23.发明申请Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage 失效实现具有增强的SRAM单元稳定性和增强区域使用的Domino读取SRAM的本地评估公开(公告)号：US20100046278A1
公开(公告)日：2010-02-25
申请号：US12195151
申请日：2008-08-20
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.
摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 实现相关SRAM单元组的读和写操作的SRAM本地评估电路包括真和补补位线，真和补写写数据传播输入，预充电信号和预充电写信号。 相应的预充电装置连接在电压源VDD与真位线和补码位线之间。 第一传递门装置连接在补码位线和真实写入数据传播输入端之间。 第二个通路装置连接在真位线和补码写入数据传播输入之间。 在读取操作期间，预充电写信号禁用通路器件。 在写入操作期间，预充电写入信号使能通路装置。
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24.发明授权公开(公告)号：US08754417B2
公开(公告)日：2014-06-17
申请号：US13608059
申请日：2012-09-10
申请人： Todd Alan Christensen , Phil Christopher Felice Paone , David Paul Paulsen , John Edward Sheets, II
发明人： Todd Alan Christensen , Phil Christopher Felice Paone , David Paul Paulsen , John Edward Sheets, II
IPC分类号： H01L29/10 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L27/092 , H01L21/743 , H01L21/84 , H01L27/0688 , H01L27/1203
摘要： Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.
摘要翻译： 产生垂直堆叠场效应晶体管（FET），其中第一FET和第二FET独立控制。 垂直堆叠的FET可以串联或并联连接，从而适合用作NAND电路或NOR电路的一部分。 在第一FET的源极和漏极上的外延生长，并且具有与第一FET的源极和漏极类似的掺杂，提供第二FET的源极和漏极。 与第一FET的源极和漏极的掺杂相反的类型的另外的外延生长为第二FET提供了一个主体。
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25.发明申请公开(公告)号：US20110248349A1
公开(公告)日：2011-10-13
申请号：US12757145
申请日：2010-04-09
申请人： Todd Alan Christensen , Phil Christopher Felice Paone , David Paul Paulsen , John Edward Sheets, II
发明人： Todd Alan Christensen , Phil Christopher Felice Paone , David Paul Paulsen , John Edward Sheets, II
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/743 , H01L21/84 , H01L27/0688 , H01L27/1203
摘要： Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.
摘要翻译： 产生垂直堆叠场效应晶体管（FET），其中第一FET和第二FET独立控制。 垂直堆叠的FET可以串联或并联连接，从而适合用作NAND电路或NOR电路的一部分。 在第一FET的源极和漏极上的外延生长，并且具有与第一FET的源极和漏极类似的掺杂，提供第二FET的源极和漏极。 与第一FET的源极和漏极的掺杂相反的类型的另外的外延生长为第二FET提供了一个主体。
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公开(公告)号：US07715221B2
公开(公告)日：2010-05-11
申请号：US12143864
申请日：2008-06-23
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/413 , G11C2207/2227
摘要： A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.
摘要翻译： 实现多米诺骨牌静态随机存取存储器（SRAM）泄漏电流降低的方法和装置包括耦合到一对本地SRAM单元组的真和补位线的局部评估电路，接收预充电信号并提供连接到全局点线 。 休眠输入被应用于SRAM休眠逻辑和包括睡眠控制的写入驱动器。 当睡眠输入转变为高电平时，写入驱动器的数据真实和数据补码输出被强制到相应的选定电平以放电位线和全局点线。 通过写入驱动器中的选通来实现位线和全局点线的放电，而不需要本地评估电路中的任何额外的器件。
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公开(公告)号：US20080273402A1
公开(公告)日：2008-11-06
申请号：US12143864
申请日：2008-06-23
CPC分类号： G11C7/12 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C11/413 , G11C2207/2227
摘要： A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.
摘要翻译： 实现多米诺骨牌静态随机存取存储器（SRAM）泄漏电流降低的方法和装置包括耦合到一对本地SRAM单元组的真和补位线的局部评估电路，接收预充电信号并提供连接到全局点线 。 休眠输入被应用于SRAM休眠逻辑和包括睡眠控制的写入驱动器。 当睡眠输入转变为高电平时，写入驱动器的数据真实和数据补码输出被强制到相应的选定电平以放电位线和全局点线。 通过写入驱动器中的选通来实现位线和全局点线的放电，而不需要本地评估电路中的任何额外的器件。
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公开(公告)号：US07218543B2
公开(公告)日：2007-05-15
申请号：US11232767
申请日：2005-09-22
IPC分类号： G11C17/00
摘要： An apparatus and method to improve a cycle time of a Read Only Memory (ROM). Loading of each bit line is controlled such that no bit line has less than a specified loading fraction of a loading of a maximally loaded bit line. No additional space or additional circuitry is required. Four NFET pair arrangements are personalizable by via placement by a designer or design automation program. One of the NFET pair arrangements is usable to pad load on a bit line without altering a logical personalization of the bit line. Proper selection from the four NFET pair arrangements ensure that no bit line has less than the specified loading fraction of the loading of the maximally loaded bit line, as well as providing proper logical personality of the bit line.
摘要翻译： 一种用于改善只读存储器（ROM）的周期时间的装置和方法。 控制每个位线的加载使得没有位线小于装载最大负载位线的指定负载分数。 不需要额外的空间或额外的电路。 四个NFET对安排可以通过设计者或设计自动化程序的放置来个性化。 NFET对布置中的一个可用于在位线上填充负载而不改变位线的逻辑个性化。 来自四个NFET对布置的适当选择确保没有位线小于最大负载位线的负载的指定负载分数，以及提供位线的适当逻辑个性。
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公开(公告)号：US07206236B1
公开(公告)日：2007-04-17
申请号：US11330693
申请日：2006-01-12
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Elizabeth Lair Gerhard , George Francis Paulik
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Elizabeth Lair Gerhard , George Francis Paulik
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： Arrays such as SRAMs, DRAMs, CAMs & Programmable ROMs having multiple independent failures are repaired using redundant bit lines. A first embodiment provides redundant bit lines on one side of the array. During a write, data is shifted towards the redundant bit lines on the one side of the array, bypassing failed bit lines. A second embodiment provides a spare bit line on each side of the array. During a write, a first failing bit line is replaced by a first spare bit line on a first side of the array, and a second failing bit line is replaced by a second spare bit line on a second side of the array.
摘要翻译： 使用冗余位线修复具有多个独立故障的诸如SRAM，DRAM，CAM和可编程ROM的阵列。 第一实施例在阵列的一侧提供冗余位线。 在写入期间，数据将朝着阵列一侧的冗余位线移动，绕过故障位线。 第二实施例在阵列的每一侧提供备用位线。 在写入期间，第一故障位线由阵列的第一侧上的第一备用位线替代，并且第二故障位线被阵列的第二侧上的第二备用位线替代。
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公开(公告)号：US07015600B2
公开(公告)日：2006-03-21
申请号：US10268287
申请日：2002-10-10
摘要： A pulse generator circuit is disclosed including a delay element coupled to a logic circuit. The delay element receives a clock signal CLK and a signal X and produces a signal XN dependent upon the clock signal CLK and the signal X. The logic circuit receives the clock signal CLK and the signal XN and produces a signal ACLK such that ACLK=CLK·XN′. The signal ACLK may include a series of positive pulses. The delay element may be, for example, one of multiple delay elements coupled in series, and signal X may be an output of a preceding one of the delay elements. A semiconductor device is described including the above pulse generator circuit and a self-resetting logic circuit. The self-resetting logic circuit receives the signal ACLK and one or more input signals and performs a logic operation using the one or more input signals during the positive pulses. The semiconductor device may include, for example, a random access memory (RAM) device, and the self-resetting logic circuit may form a part of a decoder circuit of the RAM device.
摘要翻译： 公开了一种脉冲发生器电路，其包括耦合到逻辑电路的延迟元件。 延迟元件接收时钟信号CLK和信号X，并产生取决于时钟信号CLK和信号X的信号XN。逻辑电路接收时钟信号CLK和信号XN，并产生信号ACLK，使得ACLK = CLK .XN'。 信号ACLK可以包括一系列正脉冲。 延迟元件可以是例如串联耦合的多个延迟元件中的一个，并且信号X可以是先前的一个延迟元件的输出。 描述了包括上述脉冲发生器电路和自复位逻辑电路的半导体器件。 自复位逻辑电路接收信号ACLK和一个或多个输入信号，并在正脉冲期间使用一个或多个输入信号执行逻辑运算。 半导体器件可以包括例如随机存取存储器（RAM）器件，并且自复位逻辑电路可以形成RAM器件的解码器电路的一部分。
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