公开(公告)号：US07444172B1

公开(公告)日：2008-10-28

申请号：US09457817

申请日：1999-12-09

Applicant: Dong-Jin Lee ,  Byung-Hun Hwang ,  Chul-Gyoo Park ,  Young-Seoung Joo

Inventor： Dong-Jin Lee ,  Byung-Hun Hwang ,  Chul-Gyoo Park ,  Young-Seoung Joo

IPC: H04Q7/20

CPC classification number: H04M1/6075 ,  H04M1/66

Abstract: A device and method for automatically controlling power of a radio mobile terminal connected to a hands-free kit and for preventing the radio mobile terminal from malfunctioning. In a power control method for automatically turning on a radio mobile terminal connected to a hands-free kit, the radio mobile terminal including a power control signal generator, a signal output terminal and a signal input terminal, the hands-free kit including a power-on signal generator and a signal detector, a power-on signal is supplied to the signal input terminal for a predetermined time period through the power-on signal generator when the radio mobile terminal is connected to the hands-free kit. After the predetermined time period elapses, generating the power-on signal is stopped. It is determined if the driving signal generated by the signal output terminal is detected through the signal detector. If the driving signal is detected, generating the power-on signal is stopped.

Abstract translation: 一种用于自动控制连接到免提套件的无线电移动终端的电力并防止无线电移动终端发生故障的装置和方法。 在一种用于自动接通连接到免提工具的无线电移动终端的功率控制方法中，所述无线移动终端包括功率控制信号发生器，信号输出端和信号输入端，所述免提组件包括功率 在信号发生器和信号检测器中，当无线电移动终端连接到免提套件时，通过电源接通信号发生器将电源接通信号提供给信号输入端口预定的时间段。 在经过预定时间段之后，停止产生通电信号。 确定通过信号检测器检测由信号输出端产生的驱动信号。 如果检测到驱动信号，则停止产生通电信号。

公开(公告)号：US20070200706A1

公开(公告)日：2007-08-30

申请号：US11553329

申请日：2006-10-26

Applicant: Dong-Jin Lee

Inventor： Dong-Jin Lee

IPC: G08B13/14

CPC classification number: G06K19/07749 ,  H01Q1/2225 ,  H01Q9/0407

Abstract: This invention relates to a radio frequency identification (RFID) tag and ceramic patch antenna for radio frequency identification systems. The radio frequency identification tag in accordance with this invention comprises; lower antenna member of which one end is formed with coupling projection for conjoining; upper antenna member of which one end is formed with coupling groove for conjoining; an RFID chip of which one end is conjoined with the coupling projection of the said lower antenna member and the other end is conjoined with the coupling groove of the said upper antenna member, containing the information of the objective management item which communicates with the terminal device; and a spacer which electrically isolates the said antenna members. The said antenna members are conjoined on the top and bottom sides of the said spacer in parallel direction. The RFID chip which is conjoined with the said antenna members is placed on the top or bottom side of the said spacer.The ceramic patch antenna in accordance with this invention comprises; a dielectric ceramic member formed with ceramic substance of which the permittivity is 4.0˜210 and formed with a feeder hole punched at the center; conductive film formed on one side of the said dielectric ceramic member; an earth plate affixed on the other side of the said dielectric ceramic and formed with a punched feeder hole at the center; a feeder pin which is inserted in the feeder hole of the said dielectric ceramic and contacted with and feeds electricity to the said conductive film. The said feeder pin is inserted into the feeder hole of the said dielectric ceramic. The said conductive film covers the feeder hole formed in the said dielectric ceramic and electrically contacts with the feeder pin inserted into the feeder hole, The feeder hole of the said earth plate is formed larger than the feeder hole of the said dielectric ceramic, so that electrically isolated with the said feeder pin.

公开(公告)号：US20070176657A1

公开(公告)日：2007-08-02

申请号：US11623925

申请日：2007-01-17

Applicant: Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

Inventor： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03K5/13 ,  H03K2005/00052

Abstract: A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

Abstract translation: 延迟锁定环路（DLL）电路包括备用信号发生电路，前级电路和后级电路。 待机信号发生电路响应于有效信号，一个使能信号，一个第一列地址选通（CAS）等待时间信号和一个第二CAS等待时间信号，产生第一待机信号和第二备用信号。 前级电路将外部时钟信号的相位与反馈信号的相位进行比较，并且基于外部时钟信号和反馈信号之间的相位差来延迟外部时钟信号以产生第一时钟信号。 后级电路对第一时钟信号执行内插和占空比校正。

公开(公告)号：US07239560B2

公开(公告)日：2007-07-03

申请号：US10749521

申请日：2004-01-02

Applicant: Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

Inventor： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC: G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C2207/105

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

公开(公告)号：US20060083079A1

公开(公告)日：2006-04-20

申请号：US11252535

申请日：2005-10-18

Applicant: Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

Inventor： Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

IPC: G11C16/04

CPC classification number: G11C7/1051 ,  G11C5/147 ,  G11C7/1048 ,  G11C7/1057

Abstract: A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a first power supply voltage and pulls down the output terminal to a second power supply voltage based on an output data signal. The pull-down driver pre-emphasizes an initial stage of a pull-down driving operation of the output terminal based on the output data.

Abstract translation: 数据输出缓冲器包括输出端子，缓冲器和下拉驱动器。 输出端耦合到传输线的第一端，传输线在第二端耦合到上拉终端电阻。 缓冲器将输出端上拉至第一电源电压，并根据输出数据信号将输出端拉低至第二电源电压。 下拉驱动器基于输出数据预先强调输出端子的下拉驱动操作的初始阶段。

公开(公告)号：US5701284A

公开(公告)日：1997-12-23

申请号：US492713

申请日：1995-06-20

Applicant: Dong-Jin Lee

Inventor： Dong-Jin Lee

IPC: G11B19/20 ,  G11B19/26

CPC classification number: G11B19/20 ,  G11B19/26

Abstract: An apparatus and method for rapidly controlling the disk rotation by detecting a high speed rotation and a reverse rotation of a disk. The disk driving apparatus for controlling rotation of a disk in a normal mode includes a spindle motor for driving the rotation of the disk by a spindle control signal and for generating a spindle driving voltage as the disk rotates, a servo control for generating the spindle control signal of the spindle motor by a servo control signal, a device for converting the spindle driving voltage into digital data, a device for storing a rotation range data table of the spindle driving voltage corresponding to ah abnormal rotation of the disk, and a controller for comparing and analyzing the converted digital data with the rotation range data table, sensing normal and abnormal states, and generating the servo control signal from the sensed results. Upon sensing an abnormal state the controller generates the servo control signal applying a reverse torque to a rotation direction of the spindle motor during a predetermined time, and sequentially performs a stop mode and a normal driving mode.

Abstract translation: 通过检测盘的高速旋转和反向旋转来快速控制盘旋转的装置和方法。 用于以正常模式控制盘的旋转的盘驱动装置包括主轴电机，用于通过主轴控制信号驱动盘的旋转，并且当盘旋转时产生主轴驱动电压，用于产生主轴控制的伺服控制 伺服控制信号的主轴电动机的信号，将主轴驱动电压转换为数字数据的装置，存储对应于盘的异常旋转的主轴驱动电压的旋转范围数据表的装置，以及用于 通过旋转范围数据表比较和分析转换的数字数据，检测正常和异常状态，并根据感测结果生成伺服控制信号。 在感测到异常状态时，控制器在预定时间内产生施加与主轴电动机的旋转方向相反的转矩的伺服控制信号，并且顺序地执行停止模式和正常驱动模式。

公开(公告)号：US20110184024A1

公开(公告)日：2011-07-28

申请号：US12680236

申请日：2008-09-16

Applicant: Seong-Shin Kwak ,  Bong-Sang Lee ,  Do-Woo Kwon ,  Hong Ryeol Jeon ,  Ji-Yun Moon ,  Dong-Jin Lee

Inventor： Seong-Shin Kwak ,  Bong-Sang Lee ,  Do-Woo Kwon ,  Hong Ryeol Jeon ,  Ji-Yun Moon ,  Dong-Jin Lee

IPC: A61K31/4439 ,  A61P1/04

CPC classification number: A61K31/4439 ,  A61K9/1611 ,  A61K9/2009

Abstract: The present invention relates to esomeprazole free base or its alkali salt-containing composition which stability is improved and is easy to manufacture.

Abstract translation: 本发明涉及艾美拉唑游离碱或其含有碱金属盐的组合物，其稳定性得到改善且易于制造。

公开(公告)号：US20110037504A1

公开(公告)日：2011-02-17

申请号：US12911412

申请日：2010-10-25

Applicant: Dong-Jin Lee

Inventor： Dong-Jin Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/0818 ,  H03L7/10

Abstract: A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

Abstract translation: 延迟锁定环（DLL）电路具有延迟接收到的外部时钟信号以获得精细延迟时间的第一延迟线，然后输出第一内部时钟信号; 占空比校正单元，校正第一内部时钟信号的占空比，然后输出第二时钟信号; 第二延迟线，延迟所述第二时钟信号的粗略延迟时间，然后输出第二内部时钟信号; 以及相位检测和控制单元，其检测外部时钟信号和反馈的第二内部时钟信号的相位之间的差异，并且控制精细延迟时间和粗略延迟时间。 DLL电路通过使用不同类型的延迟单元执行粗略锁定和精细锁定，从而消耗少量的功率，并且坚固地承受PVT变量的抖动和变化。

公开(公告)号：US20090121942A1

公开(公告)日：2009-05-14

申请号：US12353429

申请日：2009-01-14

Applicant: Dong-Jin Lee

Inventor： Dong-Jin Lee

IPC: H01Q1/38

CPC classification number: G06K19/07749 ,  H01Q1/2225 ,  H01Q9/0407

Abstract: This invention relates to a radio frequency identification (RFID) tag and ceramic patch antenna for radio frequency identification systems. The radio frequency identification tag in accordance with this invention comprises; lower antenna member of which one end is formed with coupling projection for conjoining; upper antenna member of which one end is formed with coupling groove for conjoining; an RFID chip of which one end is conjoined with the coupling projection of the said lower antenna member and the other end is conjoined with the coupling groove of the said upper antenna member, containing the information of the objective management item which communicates with the terminal device; and a spacer which electrically isolates the said antenna members. The said antenna members are conjoined on the top and bottom sides of the said spacer in parallel direction. The RFID chip which is conjoined with the said antenna members is placed on the top or bottom side of the said spacer.The ceramic patch antenna in accordance with this invention comprises; a dielectric ceramic member formed with ceramic substance of which the permittivity is 4.0˜210 and formed with a feeder hole punched at the center; conductive film formed on one side of the said dielectric ceramic member; an earth plate affixed on the other side of the said dielectric ceramic and formed with a punched feeder hole at the center; a feeder pin which is inserted in the feeder hole of the said dielectric ceramic and contacted with and feeds electricity to the said conductive film. The said feeder pin is inserted into the feeder hole of the said dielectric ceramic. The said conductive film covers the feeder hole formed in the said dielectric ceramic and electrically contacts with the feeder pin inserted into the feeder hole. The feeder hole of the said earth plate is formed larger than the feeder hole of the said dielectric ceramic, so that electrically isolated with the said feeder pin.

公开(公告)号：US20080304334A1

公开(公告)日：2008-12-11

申请号：US12195516

申请日：2008-08-21

Applicant: Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

Inventor： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC: G11C7/00 ,  G11C8/18 ,  H03K19/003

CPC classification number: G11C7/1051 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/105

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract translation: 具有片上终端（ODT）电路和ODT方法的同步半导体存储器件通过执行与外部同步的ODT操作，满足ODT DC和AC参数规格并通过外部或内部控制执行自适应阻抗匹配 时钟。 具有用于与外部时钟同步地进行数据输出操作的数据输出电路的同步半导体存储器件包括ODT电路，用于产生具有与用于数据输出操作的数据输出上下信号相同的定时的ODT上下信号， 执行ODT操作。