公开(公告)号：US20230281434A1

公开(公告)日：2023-09-07

申请号：US17893462

申请日：2022-08-23

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Dimitri HOUSSAMEDDINE ,  Sanjeev AGGARWAL

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/16

CPC classification number: G06N3/063 ,  G11C11/54 ,  G11C11/161

Abstract: The present disclosure is drawn to, among other things, a device comprising input circuitry; weight operation circuitry electrically connected to the input circuitry; bias operation circuitry electrically connected to the weight operation circuitry; storage circuitry electrically connected to the weight operation circuitry and the bias operation circuitry; and activation function circuitry electrically connected to the bias operation circuitry, wherein at least the weight operation circuitry, the bias operation circuitry, and the storage circuitry are located on a same chip.

公开(公告)号：US20220149271A1

公开(公告)日：2022-05-12

申请号：US17533395

申请日：2021-11-23

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry Joseph NAGEL

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.

公开(公告)号：US20210328138A1

公开(公告)日：2021-10-21

申请号：US17270151

申请日：2019-08-22

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Sarin DESHPANDE ,  Kerry NAGEL ,  Santosh KARRE

IPC: H01L43/12 ,  H01L43/02

Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.

公开(公告)号：US20210265563A1

公开(公告)日：2021-08-26

申请号：US17245882

申请日：2021-04-30

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H01L43/12 ,  B82Y25/00 ,  G01R33/00 ,  G01R33/09 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US20200373481A1

公开(公告)日：2020-11-26

申请号：US16989155

申请日：2020-08-10

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Sarin A. DESHPANDE ,  Kerry Joseph NAGEL

IPC: H01L43/12 ,  H01L27/22

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

公开(公告)号：US20200343300A1

公开(公告)日：2020-10-29

申请号：US16395396

申请日：2019-04-26

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Jijun SUN

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08

Abstract: A magnetoresistive device may include a first ferromagnetic region, a second ferromagnetic region, and an intermediate region positioned between the first ferromagnetic region and the second ferromagnetic region. The intermediate region may be formed of a dielectric material and comprise at least two different metal oxides.

公开(公告)号：US20200287128A1

公开(公告)日：2020-09-10

申请号：US16881151

申请日：2020-05-22

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Sarin A. DESHPANDE

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

公开(公告)号：US20200185602A1

公开(公告)日：2020-06-11

申请号：US16794449

申请日：2020-02-19

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason Janesky

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US20200020852A1

公开(公告)日：2020-01-16

申请号：US16580025

申请日：2019-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Kerry Joseph NAGEL ,  Chaitanya MUDIVARTHI ,  Sanjeev AGGARWAL

IPC: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US20190157550A1

公开(公告)日：2019-05-23

申请号：US16255912

申请日：2019-01-24

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason Janesky

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.