公开(公告)号：US20090292778A1

公开(公告)日：2009-11-26

申请号：US12124531

申请日：2008-05-21

申请人： MICHAEL G. MAKAR ,  Joseph M. Mosley ,  Tracy A. Tindall ,  Gene I. Kofman

发明人： MICHAEL G. MAKAR ,  Joseph M. Mosley ,  Tracy A. Tindall ,  Gene I. Kofman

IPC分类号： G06F15/16 ,  G09G5/30

CPC分类号： G06N99/005 ,  G06F9/44 ,  G06F17/30 ,  G06Q30/02

摘要： The present invention is uniquely designed to interact with web retailer's customers with real agent reaction times as they give astute answers directly concerning web retailer's products and goals. The entire process is manageable through a third-party website which includes scripting, settings and other parameters selected by the web retailer. An artificial intelligence engine uses the combination of Bayesian probability keyword selection, natural language parsing and regular expression processing. The technology updates its response database with every client interaction-learning always takes place as it simulates a live agent, in real time. Every client interaction is recorded and analyzed, and as a result of the analysis the changes in the answer database are made.

摘要翻译： 本发明独特地设计成与网络零售商的客户进行互动，具有真实的代理反应时间，因为它们直接提供有关网络零售商的产品和目标的明确答案。 整个流程可通过第三方网站进行管理，该网站包括网络零售商选择的脚本，设置和其他参数。 人工智能引擎使用贝叶斯概率关键字选择，自然语言解析和正则表达式处理的组合。 该技术随着每个客户端交互更新其响应数据库 - 学习总是在实时模拟实时代理时发生。 记录和分析每个客户端交互，并作为分析的结果，做出答案数据库中的更改。

公开(公告)号：US5821457A

公开(公告)日：1998-10-13

申请号：US902032

申请日：1997-07-29

申请人： Joseph M. Mosley ,  Maria M. Portuondo

发明人： Joseph M. Mosley ,  Maria M. Portuondo

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01L23/02

CPC分类号： H01L23/49861 ,  H01L23/50 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45138 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/4943 ,  H01L2224/85444 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011

摘要： A semiconductor die carrier includes an insulative module; a plurality of electrically conductive leads extending from the insulative module; a semiconductor die housed with the insulative module; and at least one high frequency capacitor secured to the insulative module for facilitating transmission of high frequency signals carried to and from the semiconductor die on the electrically conductive leads.

摘要翻译： 半导体管芯载体包括绝缘模块; 从所述绝缘模块延伸的多个导电引线; 与绝缘模块一起容纳的半导体管芯; 以及固定到绝缘模块的至少一个高频电容器，用于便于传输在导电引线上和从半导体管芯上传输的高频信号。

公开(公告)号：US5630058A

公开(公告)日：1997-05-13

申请号：US322627

申请日：1994-10-13

申请人： Joseph M. Mosley ,  Walter N. Zalph

发明人： Joseph M. Mosley ,  Walter N. Zalph

IPC分类号： G06F11/30 ,  G06F11/32 ,  H04L12/26

CPC分类号： G06F11/327 ,  G06F11/3051 ,  G06F11/3093

摘要： A network protection method and apparatus are disclosed for alerting an operator when a terminal device is disconnected from the network. A network controller adapter is connected to a network control computer. The network controller periodically stops normal data communication and scans some or all of the network ports to ascertain the present and absent status of a terminal device at each port. Status is detected by passing a current through a port and measuring the feedback voltage. If the status changes between scans, an operator is alerted by sounding an alarm at the network control computer or by other steps such as dialing a telephone number and transmitting a stored message or by transmitting an alarm message over the network to one of the terminal devices such as a personal computer.

摘要翻译： 公开了一种网络保护方法和装置，用于在终端设备与网络断开连接时提醒操作者。 网络控制器适配器连接到网络控制计算机。 网络控制器周期性地停止正常数据通信并扫描部分或全部网络端口，以确定每个端口上的终端设备的当前状态和不存在状态。 通过传递电流通过端口并测量反馈电压来检测状态。 如果扫描之间的状态改变，则通过在网络控制计算机处发出警报或通过诸如拨打电话号码和发送存储的消息或通过网络向其中一个终端设备发送警报消息的其他步骤来警告操作者 如个人电脑。

公开(公告)号：US4978927A

公开(公告)日：1990-12-18

申请号：US433260

申请日：1989-11-08

申请人： Kristen A. Hausman ,  Gene J. Gaudenzi ,  Joseph M. Mosley ,  Susan L. Tempest

发明人： Kristen A. Hausman ,  Gene J. Gaudenzi ,  Joseph M. Mosley ,  Susan L. Tempest

IPC分类号： H03K3/03 ,  H03K3/282

CPC分类号： H03K3/0315 ,  Y10S331/03

摘要： Each section (e.g., 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (FIG. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e.g., 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be disabled, thereby removing the remaining sections (106) of the oscillator from the closed loop path. The NOR gates are implemented as a differential amplifier (FIG. 5) having two transistors (610 and 612) in the input leg and one transistor (616) with its base connected to a regulated voltage (Vr) in the opposite leg. The output of the NOR gate is taken from the collectors of the input transistors. The propagation delay of the oscillator signal through the gate is minimal because, to switch the output state of the gate, only the state of one of the input transistors (610 or 612) must be changed. The short propagation delay through the gate permits high frequency operation, as well as the ability to program small incremental steps in the center frequency of the oscillator.

公开(公告)号：US4833425A

公开(公告)日：1989-05-23

申请号：US173517

申请日：1988-03-25

申请人： Edward F. Culican, Sr. ,  John D. Davis ,  John F. Ewen ,  Scott A. Mc Cabe ,  Joseph M. Mosley ,  Allan L. Mullgrav, Jr. ,  Philip F. Noto ,  Clarence I. Peterson, Jr. ,  Philip E. Pritzlaff, Jr.

发明人： Edward F. Culican, Sr. ,  John D. Davis ,  John F. Ewen ,  Scott A. Mc Cabe ,  Joseph M. Mosley ,  Allan L. Mullgrav, Jr. ,  Philip F. Noto ,  Clarence I. Peterson, Jr. ,  Philip E. Pritzlaff, Jr.

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23

CPC分类号： H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/0995 ,  H03L7/23

摘要： A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

公开(公告)号：US4529894A

公开(公告)日：1985-07-16

申请号：US273706

申请日：1981-06-15

申请人： Yuen H. Chan ,  James E. Dickerson ,  Walter S. Klara ,  Theodore W. Kwap ,  Joseph M. Mosley

发明人： Yuen H. Chan ,  James E. Dickerson ,  Walter S. Klara ,  Theodore W. Kwap ,  Joseph M. Mosley

IPC分类号： H03K5/12 ,  H03K17/04 ,  H03K19/013 ,  H03K19/086 ,  H03K19/01 ,  H03K19/082

CPC分类号： H03K19/0136

摘要： Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node. As a result, the transition time involved in going from one voltage level to another at the output node is substantially reduced.

摘要翻译： 公开了用于增强逻辑电路性能的手段，更具体地说，用于增强各种逻辑电路的切换速度。 所涉及的是将所谓的“卡扣”或增强型晶体管插入连接到限定基本逻辑电路的输出的公共节点。 在一个示例中，该“捕捉”晶体管的发射极连接到电路中的输出节点，其在常规实践中将在上行转换期间被固定的RC时间常数充电。 然而，根据本发明的改进，由于存储在其中的电荷，“卡扣”晶体管保持导通，尽管关联的逻辑器件被关断。 该电流作为反向基极电流放电，并且输出提供看起来是感应电压尖峰。 效果是临时的电流源可用于对公共节点充电。 结果，显着减少了在输出节点从一个电压电平转到另一个电压电平的过渡时间。