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21.发明申请TOP ELECTRODE COUPLING IN A MAGNETORESISTIVE DEVICE USING AN ETCH STOP LAYER 有权使用蚀刻停止层的磁性器件中的顶部电极耦合公开(公告)号：US20150357559A1
公开(公告)日：2015-12-10
申请号：US14297389
申请日：2014-06-05
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph Nagel , Sanjeev Aggarwal , Moazzem Hossain , Nicholas Rizzo
CPC classification number: H01L27/222 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/12
Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.
Abstract translation: 在磁阻堆叠的底部电极和侧壁上方的氮化硅层用作磁阻器件的制造期间的绝缘体和蚀刻停止。 非选择性化学机械抛光除了用于器件的顶部电极以及用于封装的二氧化硅之外的任何氮化硅。 对应于形成通孔以到达顶部电极的后来的蚀刻操作使用去除二氧化硅以进入顶部电极但是不去除氮化硅的选择性蚀刻化学品。 因此，氮化硅用作蚀刻停止，并且在所得到的器件中提供了防止通孔和底部电极之间以及磁阻器件堆叠的通路和侧壁之间的不期望的短路的绝缘层。
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22.发明授权Apparatus and process for manufacturing ST-MRAM having a metal oxide tunnel barrier 有权用于制造具有金属氧化物隧道势垒的ST-MRAM的装置和方法公开(公告)号：US09136464B1
公开(公告)日：2015-09-15
申请号：US14037087
申请日：2013-09-25
Applicant: Everspin Technologies, Inc.
Inventor： Renu Whig , Jason Janesky , Nicholas Rizzo , Jon Slaughter , Dimitri Houssameddine
CPC classification number: H01L43/02 , B82Y10/00 , H01L27/222 , H01L43/08 , H01L43/10 , H01L43/12 , Y10S977/935
Abstract: An MRAM device, and a process for manufacturing the device, provides improved breakdown distributions, a reduced number of bits with a low breakdown voltage, and an increased MR, thereby improving reliability, manufacturability, and error-free operation. A tunnel barrier is formed between a free layer and a fixed layer in three repeating steps of forming a metal material, interceded by oxidizing each of the metal materials. The oxidization of the third metal material is greater than the dose of the first metal, but less than the dose of the second metal. The fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.
Abstract translation: MRAM器件以及用于制造器件的工艺提供了改进的击穿分布，具有低击穿电压的位数减少以及增加的MR，从而提高了可靠性，可制造性和无错误操作。 在自由层和固定层之间形成隧道势垒，在三个重复步骤中形成金属材料，通过氧化每种金属材料进行交换。 第三金属材料的氧化大于第一金属的剂量，但小于第二金属的剂量。 固定层可以在两层铁磁材料之间的固定层中包括不连续的金属层，例如Ta。
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23.发明申请TWO-AXIS MAGNETIC FIELD SENSOR HAVING REDUCED COMPENSATION ANGLE FOR ZERO OFFSET 有权具有减速补偿角度的双轴磁场传感器用于零偏移公开(公告)号：US20140159179A1
公开(公告)日：2014-06-12
申请号：US14168095
申请日：2014-01-30
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Jijun Sun , Phillip Mather , Srinivas Pietambaram , Jon Slaughter , Renu Whig , Nicholas Rizzo
CPC classification number: H01L43/10 , G01R33/098 , H01L43/12 , Y10T29/49117
Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.
Abstract translation: 提供传感器和制造工艺，用于形成具有基本上正交的磁化方向的参考层，具有零偏移并具有小的补偿角。 示例性实施例包括基于磁阻薄膜的磁场传感器的传感器层堆叠，传感器层堆叠包括钉扎层; 包括在钉扎层上的无定形材料层的钉扎层和在非晶材料层上的第一层结晶材料; 在被钉扎层上的非磁性耦合层; 在非磁耦合层上的固定层; 固定层上的隧道势垒; 以及在非磁性中间层上的感测层。 另一个实施例包括传感器层堆叠，其中包括由非晶层隔开的两个结晶层的钉扎层。
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公开(公告)号：US20140138346A1
公开(公告)日：2014-05-22
申请号：US13972637
申请日：2013-08-21
Applicant: EverSpin Technologies, Inc.
Inventor： Renu Whig , Philip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
CPC classification number: H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。
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25.发明授权Two-axis magnetic field sensor having reduced compensation angle for zero offset 有权两轴磁场传感器具有减小零偏移的补偿角公开(公告)号：US08647891B2
公开(公告)日：2014-02-11
申请号：US13909622
申请日：2013-06-04
Applicant: Everspin Technologies, Inc.
Inventor： Jijun Sun , Phillip Mather , Srinivas Pietambaram , Jon Slaughter , Renu Whig , Nicholas Rizzo
IPC: H01L21/00
CPC classification number: H01L43/10 , G01R33/098 , H01L43/12 , Y10T29/49117
Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.
Abstract translation: 提供传感器和制造工艺，用于形成具有基本上正交的磁化方向的参考层，具有零偏移并具有小的补偿角。 示例性实施例包括基于磁阻薄膜的磁场传感器的传感器层堆叠，传感器层堆叠包括钉扎层; 包括在钉扎层上的无定形材料层的钉扎层和在非晶材料层上的第一层结晶材料; 在被钉扎层上的非磁性耦合层; 在非磁耦合层上的固定层; 固定层上的隧道势垒; 以及在非磁性中间层上的感测层。 另一个实施例包括传感器层堆叠，其中包括由非晶层隔开的两个结晶层的钉扎层。
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Patent Agency Ranking
公开(公告)号：US11678584B2
公开(公告)日：2023-06-13
申请号：US17245882
申请日：2021-04-30
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Renu Whig , Phillip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
CPC classification number: H10N50/01 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H10B61/00 , H10N50/10 , H10N50/80 , H10N59/00
Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
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公开(公告)号：USRE49404E1
公开(公告)日：2023-01-31
申请号：US15470997
申请日：2017-03-28
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Phillip Mather , Jon Slaughter , Nicholas Rizzo
Abstract: Three bridge circuits (101, 111, 121), each include magnetoresistive sensors coupled as a Wheatstone bridge (100) to sense a magnetic field (160) in three orthogonal directions (110, 120, 130) that are set with a single pinning material deposition and bulk wafer setting procedure. One of the three bridge circuits (121) includes a first magnetoresistive sensor (141) comprising a first sensing element (122) disposed on a pinned layer (126), the first sensing element (122) having first and second edges and first and second sides, and a first flux guide (132) disposed non-parallel to the first side of the substrate and having an end that is proximate to the first edge and on the first side of the first sensing element (122). An optional second flux guide (136) may be disposed non-parallel to the first side of the substrate and having an end that is proximate to the second edge and the second side of the first sensing element (122).
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公开(公告)号：US10347828B2
公开(公告)日：2019-07-09
申请号：US16230031
申请日：2018-12-21
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Renu Whig , Jijun Sun , Nicholas Rizzo , Jon Slaughter , Dimitri Houssameddine , Frederick Mancoff
Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
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公开(公告)号：US20180226574A1
公开(公告)日：2018-08-09
申请号：US15941153
申请日：2018-03-30
Applicant: Everspin Technologies, Inc.
Inventor： Renu Whig , Jijun Sun , Nicholas Rizzo , Jon Slaughter , Dimitri Houssameddine , Frederick Mancoff
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
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公开(公告)号：US09728583B2
公开(公告)日：2017-08-08
申请号：US15249559
申请日：2016-08-29
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph Nagel , Sanjeev Aggarwal , Moazzem Hossain , Nicholas Rizzo
CPC classification number: H01L27/222 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/12
Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.
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