公开(公告)号：US20050227461A1

公开(公告)日：2005-10-13

申请号：US11144727

申请日：2005-06-02

申请人： Richard Francis ,  Chiu Ng

发明人： Richard Francis ,  Chiu Ng

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/739

CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/7395

摘要： A semiconductor device is formed in a thin float zone wafer. Junctions are diffused into the top surface of the wafer and the wafer is then reduced in thickness by removal of material from its bottom surface. A weak collector is then formed in the bottom surface by diffusion of boron (for a P type collector). The weak collector is then formed or activated only over spaced or intermittent areas. This is done by implant of the collector impurity through a screening mask; or by activating only intermittent areas by a laser beam anneal in which the beam is directed to anneal only preselected areas. The resulting device has an effective very low implant dose, producing a reduced switching energy and increased switching speed, as compared to prior art weak collector/anodes and life time killing technologies.

摘要翻译： 半导体器件形成在薄浮动区晶片中。 结点扩散到晶片的顶表面，然后通过从其底表面去除材料来减小晶片的厚度。 然后通过硼的扩散（用于P型收集器）在底表面中形成弱集电体。 然后，弱集电器仅在间隔或间断区域形成或激活。 这是通过通过掩模掩模注入收集器杂质完成的; 或者仅通过激光束退火仅激活间歇区域，其中光束被引导以退火仅预选区域。 与现有技术的弱收集器/阳极和寿命杀死技术相比，所得到的器件具有有效的非常低的注入剂量，产生降低的开关能量和增加的开关速度。

公开(公告)号：US06919248B2

公开(公告)日：2005-07-19

申请号：US10389857

申请日：2003-03-14

申请人： Richard Francis ,  Chiu Ng

发明人： Richard Francis ,  Chiu Ng

IPC分类号： H01L21/265 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L31/062 ,  H01L21/425

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/66348 ,  H01L29/7397

摘要： An insulated gate trench type semiconductor device having L-shaped diffused regions, each diffused region having a vertically oriented portion and a horizontally oriented portion extending laterally from the vertically oriented portion, and a method for manufacturing the device in which the vertically oriented portion of each L-shaped diffused region is formed by directing dopants at an angle toward a sidewall of a trench to form the vertically oriented portion using the edge of the opposing sidewall of the trench as a mask.

摘要翻译： 一种具有L形扩散区域的绝缘栅沟槽型半导体器件，每个扩散区域具有垂直取向部分和从垂直取向部分横向延伸的水平取向部分，以及制造该器件的方法，其中每个 通过使用沟槽的相对侧壁的边缘作为掩模将掺杂剂以一定角度引导到沟槽的侧壁以形成垂直取向的部分来形成L形扩散区域。

公开(公告)号：US06683331B2

公开(公告)日：2004-01-27

申请号：US10132549

申请日：2002-04-25

申请人： Richard Francis ,  Chiu Ng

发明人： Richard Francis ,  Chiu Ng

IPC分类号： H01L2974

CPC分类号： H01L29/7397 ,  H01L29/0834 ,  H01L29/1095

摘要： An IGBT has parallel spaced trenches lined with gate oxide and filled with conductive polysilicon gate bodies. The trenches extend through a P− base region which is about 7 microns deep. A deep narrow N+ emitter diffusion is at the top of the trench and a shallow P+ contact diffusion extends between adjacent emitter diffusions. The N+ emitter diffusions are arranged to define a minimum RB′. The trenches are sufficiently deep to define long channel regions which can withstand a substantial portion of the blocking voltage of the device. A second blanket emitter implant and diffusion defines a shallow high concentration emitter diffusion extension at the top of the die for improved contact to the emitter diffusions.

摘要翻译： IGBT具有与栅极氧化物排列并且填充有导电多晶硅栅极体的平行隔开的沟槽。 沟槽延伸穿过大约7微米深的P'基底区域。 深沟N +发射体扩散在沟槽的顶部，浅的P +接触扩散在相邻的发射极扩散之间延伸。 N +发射极扩散布置成限定最小RB'。 沟槽足够深以限定可以承受器件的大部分阻断电压的长通道区域。 第二个覆盖发射器的注入和扩散在芯片的顶部限定了一个浅的高浓度发射极扩散延伸，以改善与发射极扩散的接触。

公开(公告)号：US08067797B2

公开(公告)日：2011-11-29

申请号：US12252684

申请日：2008-10-16

申请人： Chiu Ng ,  Yuan-Heng Chao

发明人： Chiu Ng ,  Yuan-Heng Chao

IPC分类号： H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0839 ,  H01L29/1095

摘要： A trench type IGBT as disclosed herein includes a plurality of channel regions having one threshold voltage for the normal operation of the device and a plurality of channel regions having a threshold voltage higher than the threshold voltage for the normal operation of the device.

摘要翻译： 本文公开的沟槽型IGBT包括具有用于器件的正常操作的一个阈值电压的多个沟道区域和具有高于用于器件的正常操作的阈值电压的阈值电压的多个沟道区域。

公开(公告)号：US07534666B2

公开(公告)日：2009-05-19

申请号：US11190602

申请日：2005-07-27

申请人： Richard Francis ,  Chiu Ng

发明人： Richard Francis ,  Chiu Ng

IPC分类号： H01L21/332

CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/41725 ,  H01L29/66333 ,  Y10S438/904

摘要： A process for forming an NPT IGBT in a thin N type silicon wafer in which the bottom surface of a thin silicon wafer (100 microns thick or less) has a shallow reduced lifetime region in its bottom formed by a light species atom implant to a depth of less than about 2.5 microns. A P+ transparent collector region about 0.5 microns deep is formed in the bottom of the damaged region by a boron implant. A collector contact of Al/Ti/NiV and Ag is sputtered onto the collector region and is annealed at 200° C. to 400° C. for 30 to 60 minutes. A pre-anneal step before applying the collector metal can be carried out in vacuum at 300° C. to 400° C. for 30 to 60 seconds.

摘要翻译： 一种用于在薄N型硅晶片中形成NPT IGBT的工艺，其中薄硅晶片（100微米厚或更小）的底表面在其底部具有浅的减少的寿命区域，其通过光物质原子注入形成深度 小于约2.5微米。 通过硼注入在损伤区域的底部形成约0.5微米深的P +透明集电极区域。 将Al / Ti / NiV和Ag的集电极触点溅射到集电极区域，并在200℃至400℃退火30至60分钟。 在施加集电体金属之前的预退火步骤可以在300℃至400℃的真空中进行30至60秒。

公开(公告)号：US07335947B2

公开(公告)日：2008-02-26

申请号：US11137040

申请日：2005-05-24

申请人： Richard Francis ,  Chiu Ng

发明人： Richard Francis ,  Chiu Ng

IPC分类号： H01L21/74 ,  H01L29/06 ,  H01L29/36

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/66348 ,  H01L29/7397

摘要： An insulated gate trench type semiconductor device having L-shaped diffused regions, each diffused region having a vertically oriented portion and a horizontally oriented portion extending laterally from the vertically oriented portion, and a method for manufacturing the device in which the vertically oriented portion of each L-shaped diffused region is formed by directing dopants at an angle toward a sidewall of a trench to form the vertically oriented portion using the edge of the opposing sidewall of the trench as a mask.

摘要翻译： 一种具有L形扩散区域的绝缘栅沟槽型半导体器件，每个扩散区域具有垂直取向部分和从垂直取向部分横向延伸的水平取向部分，以及制造该器件的方法，其中每个 通过使用沟槽的相对侧壁的边缘作为掩模将掺杂剂以一定角度引导到沟槽的侧壁以形成垂直取向的部分来形成L形扩散区域。

公开(公告)号：US20070085148A1

公开(公告)日：2007-04-19

申请号：US11252642

申请日：2005-10-18

申请人： Chiu Ng ,  Davide Chiola

发明人： Chiu Ng ,  Davide Chiola

IPC分类号： H01L31/00

CPC分类号： H01L29/7397 ,  H01L29/402 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less than 10 m ohm cm; a buffer layer thickness of about 8 μm resistivity in the range of 0.05 to 0.10 ohm cm, and an epi layer for receiving junction patterns and trenches, which has a thickness of from 31 to 37 μm and resistivity in te range of 14 to 18 ohm cm.

摘要翻译： 用于控制对等离子体显示面板的电力施加的IGBT具有增加的导电能力和降低的传导损耗，而降低安全操作区域。 对于具有300伏击穿电压额定值的器件，裸片具有小于10mΩcm的衬底电阻; 具有约0.05μm至0.10欧姆cm范围内的约8μm电阻率的缓冲层厚度，以及用于接收结形图案和沟槽的外延层，其厚度为31至37μm，电阻率范围为14至18欧姆 厘米。

公开(公告)号：US20070063269A1

公开(公告)日：2007-03-22

申请号：US11230969

申请日：2005-09-20

申请人： Chiu Ng ,  David Chiola

发明人： Chiu Ng ,  David Chiola

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L29/7397 ,  H01L29/66348

摘要： A trench type IGBT has a gate oxide lining the side walls and bottom of the trench which have a thickness greater than 1500Å and in the range of 1800Å to 2500Å, and preferably 2000Å to increase the device short circuit capability.

摘要翻译： 沟槽型IGBT具有衬在沟槽的侧壁和底部的栅极氧化物，其厚度大于1500埃，并且在1800至2500埃的范围内，优选地为2000埃，以增加器件的短路能力。

公开(公告)号：US20060094179A1

公开(公告)日：2006-05-04

申请号：US11297571

申请日：2005-12-08

申请人： Richard Francis ,  Chiu Ng ,  Hamilton Lu ,  Ranadeep Dutta

发明人： Richard Francis ,  Chiu Ng ,  Hamilton Lu ,  Ranadeep Dutta

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

摘要： The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.

公开(公告)号：US20050212039A1

公开(公告)日：2005-09-29

申请号：US11137040

申请日：2005-05-24

申请人： Richard Francis ,  Chiu Ng

发明人： Richard Francis ,  Chiu Ng

IPC分类号： H01L21/265 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/66348 ,  H01L29/7397

摘要： An insulated gate trench type semiconductor device having L-shaped diffused regions, each diffused region having a vertically oriented portion and a horizontally oriented portion extending laterally from the vertically oriented portion, and a method for manufacturing the device in which the vertically oriented portion of each L-shaped diffused region is formed by directing dopants at an angle toward a sidewall of a trench to form the vertically oriented portion using the edge of the opposing sidewall of the trench as a mask.