公开(公告)号：US07005702B1

公开(公告)日：2006-02-28

申请号：US09566219

申请日：2000-05-05

申请人： Richard Francis ,  Chiu Ng ,  Hamilton Lu ,  Ranadeep Dutta

发明人： Richard Francis ,  Chiu Ng ,  Hamilton Lu ,  Ranadeep Dutta

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

摘要： The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.

公开(公告)号：US20060094179A1

公开(公告)日：2006-05-04

申请号：US11297571

申请日：2005-12-08

申请人： Richard Francis ,  Chiu Ng ,  Hamilton Lu ,  Ranadeep Dutta

发明人： Richard Francis ,  Chiu Ng ,  Hamilton Lu ,  Ranadeep Dutta

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

摘要： The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.

公开(公告)号：US07507608B2

公开(公告)日：2009-03-24

申请号：US11297571

申请日：2005-12-08

申请人： Richard Francis ,  Chiu Ng ,  Hamilton Lu ,  Ranadeep Dutta

发明人： Richard Francis ,  Chiu Ng ,  Hamilton Lu ,  Ranadeep Dutta

IPC分类号： H01L21/332

CPC分类号： H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

摘要： The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.

摘要翻译： 形成在浮动区硅晶片中的非穿通IGBT的集电极或阳极由沉积在超薄晶片的背表面上的P掺杂非晶硅层形成。 在形成底部结构之前，在晶片的顶表面上形成DMOS结构。 在非晶硅层上形成背接触。 不需要合金步骤来激活由P型非晶硅限定的阳极。

公开(公告)号：US20120228699A1

公开(公告)日：2012-09-13

申请号：US13044997

申请日：2011-03-10

申请人： Hamilton Lu ,  Laszlo Lipcsei

发明人： Hamilton Lu ,  Laszlo Lipcsei

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

摘要： A transistor and a method of fabricating a transistor, including a metal oxide deposited on an epitaxial layer, a photo resist deposited and patterned over the metal oxide and the metal oxide and epitaxial layer are etched to form at least one circular trench, wherein the trench surfaces are defined by the epitaxial layer. An oxide layer is grown on the trench surfaces of each trench, and a gate conductor is formed within the at least one trench.

摘要翻译： 蚀刻晶体管和制造晶体管的方法，该晶体管包括沉积在外延层上的金属氧化物，在金属氧化物和金属氧化物和外延层上沉积和图案化的光致抗蚀剂以形成至少一个圆形沟槽，其中沟槽 表面由外延层限定。 在每个沟槽的沟槽表面上生长氧化物层，并且在至少一个沟槽内形成栅极导体。

公开(公告)号：US20110049682A1

公开(公告)日：2011-03-03

申请号：US12873147

申请日：2010-08-31

申请人： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

发明人： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

IPC分类号： H01L29/06 ,  H01L21/203 ,  H01L21/302

CPC分类号： H01L21/2205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/02694 ,  H01L29/16 ,  H01L29/365 ,  H01L29/7813

摘要： Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

摘要翻译： 衬底晶圆背面和边缘截面密封的系统和方法。 根据第一方法实施例，访问第一导电类型的硅晶片。 第一导电类型的外延层生长在硅晶片的前表面上。 植入外延层以形成相反导电类型的区域。 重复生长和植入以形成相反导电类型的垂直柱。 也可以将晶片植入以形成与垂直柱垂直对准的相反导电类型的区域。

公开(公告)号：US06602786B2

公开(公告)日：2003-08-05

申请号：US10082532

申请日：2002-02-21

申请人： Hamilton Lu

发明人： Hamilton Lu

IPC分类号： H01L2144

CPC分类号： H01L21/324 ,  H01L21/28061 ,  H01L29/4933

摘要： A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by forming a titanium layer atop the amorphous silicon. A single RTA process at a temperature below the temperature of contamination diffusion is carried out, preferably at about 650° C. for 30 seconds. The top of the annealed titanium silicide layer is then stripped, and the remaining layer has a sheet Rho of less than about 2 ohms per square.

公开(公告)号：US09230810B2

公开(公告)日：2016-01-05

申请号：US12873147

申请日：2010-08-31

申请人： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

发明人： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

IPC分类号： H01L21/322 ,  H01L21/20 ,  H01L21/22 ,  H01L29/78

CPC分类号： H01L21/2205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/02694 ,  H01L29/16 ,  H01L29/365 ,  H01L29/7813

摘要： Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

摘要翻译： 衬底晶圆背面和边缘截面密封的系统和方法。 根据第一方法实施例，访问第一导电类型的硅晶片。 第一导电类型的外延层生长在硅晶片的前表面上。 植入外延层以形成相反导电类型的区域。 重复生长和植入以形成相反导电类型的垂直柱。 也可以将晶片植入以形成与垂直柱垂直对准的相反导电类型的区域。

公开(公告)号：US08754472B2

公开(公告)日：2014-06-17

申请号：US13044997

申请日：2011-03-10

申请人： Hamilton Lu ,  Laszlo Lipcsei

发明人： Hamilton Lu ,  Laszlo Lipcsei

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

摘要： A transistor and a method of fabricating a transistor, including a metal oxide deposited on an epitaxial layer, a photo resist deposited and patterned over the metal oxide and the metal oxide and epitaxial layer are etched to form at least one circular trench, wherein the trench surfaces are defined by the epitaxial layer. An oxide layer is grown on the trench surfaces of each trench, and a gate conductor is formed within the at least one trench.

摘要翻译： 蚀刻晶体管和制造晶体管的方法，该晶体管包括沉积在外延层上的金属氧化物，在金属氧化物和金属氧化物和外延层上沉积和图案化的光致抗蚀剂以形成至少一个圆形沟槽，其中沟槽 表面由外延层限定。 在每个沟槽的沟槽表面上生长氧化物层，并且在至少一个沟槽内形成栅极导体。