公开(公告)号：US20190214469A1

公开(公告)日：2019-07-11

申请号：US15866855

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L29/417 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/48

CPC classification number: H01L29/41733 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/481 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0665

Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.

公开(公告)号：US20190148240A1

公开(公告)日：2019-05-16

申请号：US16243863

申请日：2019-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

公开(公告)号：US20190123162A1

公开(公告)日：2019-04-25

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US10236296B1

公开(公告)日：2019-03-19

申请号：US15861097

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Chanemougame ,  Emilie Bourjot ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L23/535

Abstract: An IC product disclosed herein includes a first merged doped source/drain (MDSD) region having an upper surface, a first side surface and a second side surface that intersect one another at a corner of the first merged doped source/drain region, a second MDSD region and a contact trench in an isolation structure positioned between the first and second MDSD regions. The product also includes a conductive gate structure positioned above at least the second MDSD region and a cross-coupled contact structure that comprises a first portion positioned within the contact trench laterally adjacent to and conductively coupled to at least one of the first side surface and the second side surface, and a second portion that is positioned above and conductively coupled to the upper surface of the MDSD region, wherein the cross-coupled contact structure is conductively coupled to the conductive gate structure.

公开(公告)号：US20190035692A1

公开(公告)日：2019-01-31

申请号：US15658524

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars W. Liebmann ,  Bipul C. Paul ,  Daniel Chanemougame ,  Nigel G. Cave

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a first gate structure above a first region of a semiconducting substrate. A first sidewall spacer is formed adjacent the first gate structure. The first gate structure and the first sidewall spacer are recessed to define a first gate contact cavity. A second sidewall spacer is formed in the first gate contact cavity. A first conductive gate contact is formed in the first gate contact cavity. The second sidewall spacer is removed to define a first spacer cavity. A conductive material is formed in the first spacer cavity to form a first conductive spacer contacting the first conductive gate contact.

公开(公告)号：US10109636B2

公开(公告)日：2018-10-23

申请号：US15453124

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Bipul C. Paul

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/3213 ,  H01L21/768

Abstract: A method of forming an active contact-gate contact interconnect including forming a first gate contact to a first gate electrode in an active region in a substrate, forming a first active contact to another portion of the first active region. The first gate contact and the first active contact include an approximately equal surface area, and forming an interconnect between the first active contact and the first gate contact. The interconnect includes a first metal wire in a first metal layer electrically connecting the first active contact to the first gate contact. The method may also include forming a second metal wire in the first metal layer configured to electrically connect a third metal wire in a second metal layer to an external contact to a second active region in the substrate, the external contact including the approximately equal surface area.

公开(公告)号：US20180261604A1

公开(公告)日：2018-09-13

申请号：US15453124

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L27/1104 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207

Abstract: A method of forming an active contact-gate contact interconnect including forming a first gate contact to a first gate electrode in an active region in a substrate, forming a first active contact to another portion of the first active region. The first gate contact and the first active contact include an approximately equal surface area, and forming an interconnect between the first active contact and the first gate contact. The interconnect includes a first metal wire in a first metal layer electrically connecting the first active contact to the first gate contact. The method may also include forming a second metal wire in the first metal layer configured to electrically connect a third metal wire in a second metal layer to an external contact to a second active region in the substrate, the external contact including the approximately equal surface area.

公开(公告)号：US09825032B1

公开(公告)日：2017-11-21

申请号：US15360537

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Bipul C. Paul

IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

公开(公告)号：US10811069B2

公开(公告)日：2020-10-20

申请号：US16248279

申请日：2019-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Harsh N. Patel ,  Bipul C. Paul

IPC: G11C11/16 ,  G11C13/00 ,  H01L27/092 ,  H01L27/22 ,  H01L27/24 ,  H01L23/528 ,  H01L29/423 ,  H01L21/8238 ,  H01L43/02 ,  H01F10/32

Abstract: Structures for a non-volatile memory and methods for forming and using such structures. The structure includes a bitcell having a non-volatile memory element and a transmission gate. The transmission gate includes an n-type field-effect transistor and a p-type field effect transistor. The n-type field-effect transistor has a first drain region, a first source region, and a first gate electrode. The p-type field-effect transistor has a second drain region, a second source region coupled in parallel with the first source region, and a second gate electrode. The first drain region of the n-type field-effect transistor and the second drain region of the p-type field-effect transistor are coupled in parallel with the non-volatile memory element.

公开(公告)号：US10720391B1

公开(公告)日：2020-07-21

申请号：US16240335

申请日：2019-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Lars W. Liebmann ,  Ruilong Xie

IPC: H01L23/00 ,  H01L23/535 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L27/11 ,  H01L21/02 ,  H01L29/66

Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.