公开(公告)号：US20170338235A1

公开(公告)日：2017-11-23

申请号：US15160591

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Manfred ELLER ,  Min-hwa CHI

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/7856

Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor. In another embodiment, the first transistor includes a fin structure extending from the substrate, and an upper portion of the fin structure includes the first channel region and a lower portion of the fin structure includes the isolation region.

公开(公告)号：US20170250284A1

公开(公告)日：2017-08-31

申请号：US15053867

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanzhen WANG ,  Jidong HUANG ,  Hui ZANG

IPC: H01L29/78 ,  H01L29/49 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/28008 ,  H01L21/2855 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: An angled gas cluster ion beam is used for each sidewall and top of a fin (two applications) to form work-function metal layer(s) only on the sidewalls and top of each fin.

公开(公告)号：US20170170293A1

公开(公告)日：2017-06-15

申请号：US15443522

申请日：2017-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/78

CPC classification number: G01P15/00 ,  G01C22/006 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one fin; forming at least one sacrificial gate with at least one barrier layer; forming a first set of spacers adjacent to the at least one sacrificial gate; forming at least one second set of spacers adjacent to the first set of spacers; and etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170033113A1

公开(公告)日：2017-02-02

申请号：US14814322

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L27/108 ,  H01L29/66

CPC classification number: H01L27/10826 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/10888 ,  H01L28/90 ,  H01L29/66545

Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, fin(s) coupled to the substrate and surrounded at a bottom portion thereof by isolation material, each fin including a source region, a drain region and a channel region therebetween, a first gate and spacers over a portion of each fin, and a second gate and spacers, the second gate encompassing a common end portion of each fin. The first gate and corresponding source and drain regions act as an access transistor, and the second gate and common end portion(s) of the fin(s) act as a storage capacitor, and a top surface of the second gate acts as a plate for the storage capacitor, when multiple cells are arranged in an array.

Abstract translation: 三维半导体器件包括：半导体衬底，耦合到衬底的鳍状物，并在其底部被隔离材料包围，每个散热片包括源极区，漏极区和它们之间的沟道区，第一栅极和 每个翅片的一部分上的间隔物，以及第二栅极和间隔物，第二栅极包围每个鳍片的共同端部。 第一栅极和相应的源极和漏极区域用作存取晶体管，并且鳍片的第二栅极和共同端部部分用作存储电容器，并且第二栅极的顶表面用作板 对于存储电容器，当多个单元被排列成阵列时。

公开(公告)号：US20160365451A1

公开(公告)日：2016-12-15

申请号：US14735283

申请日：2015-06-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

Abstract translation: 提供了用于鳍式场效应晶体管（FinFet）器件的生长非成形外延的器件和方法。 一种方法包括例如：获得具有至少一个源，至少一个漏极和至少一个鳍片的晶片; 蚀刻以暴露所述至少一个翅片的至少一部分; 形成至少一个牺牲栅结构; 以及在所述至少一个翅片上形成外延生长的第一层。 一个装置包括例如：具有至少一个源的晶片，至少一个漏极和至少一个鳍片; 在所述至少一个翅片上的外延生长的第一层; 外延生长的至少一个第二层叠加第一层外延生长; 以及在所述至少一个源极上的第一接触区域和在所述至少一个漏极上的第二接触区域。

公开(公告)号：US20160293715A1

公开(公告)日：2016-10-06

申请号：US15185801

申请日：2016-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/41725 ,  H01L21/28 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/088 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.

公开(公告)号：US20160225901A1

公开(公告)日：2016-08-04

申请号：US15091910

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/161 ,  H01L27/12 ,  H01L29/10 ,  H01L29/16 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7838 ,  H01L21/0217 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.

Abstract translation: 在一个方面，这里提出了具有从超薄体（UTB）向上延伸的翅片的半导体结构。 在一个实施例中，多层结构可以设置在晶片上，并且可用于图案从晶片的UTB层延伸的空隙。 所选择的材料可以形成在空隙中以限定从UTB层向上延伸的翅片。 在一个实施例中，硅（Si）可以在空隙内生长以限定翅片。 在一个实施例中，锗基材料可以在空隙内生长以限定翅片。

公开(公告)号：US20160225667A1

公开(公告)日：2016-08-04

申请号：US14609271

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L29/41725 ,  H01L21/28 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/088 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.

Abstract translation: 这里阐述制造半导体结构的方法，该方法包括在源/漏区上形成导电金属层。 导电金属层在一个方面可以防止在去除源极/漏极区域之上的材料时源极/漏极区的气泡。 一方面的导电金属层可以用于图案化空气间隔物以降低寄生电容。 导电金属层在一个方面可以降低源极/漏极区域和源极/漏极区域之上的接触点之间的接触电阻。

公开(公告)号：US20160118386A1

公开(公告)日：2016-04-28

申请号：US14525763

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/161 ,  H01L29/16

CPC classification number: H01L29/7838 ,  H01L21/0217 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161

Abstract: In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.

Abstract translation: 在一个方面，这里提出了具有从超薄体（UTB）向上延伸的翅片的半导体结构。 在一个实施例中，多层结构可以设置在晶片上，并且可用于图案从晶片的UTB层延伸的空隙。 所选择的材料可以形成在空隙中以限定从UTB层向上延伸的翅片。 在一个实施例中，硅（Si）可以在空隙内生长以限定翅片。 在一个实施例中，锗基材料可以在空隙内生长以限定翅片。

公开(公告)号：US20160118304A1

公开(公告)日：2016-04-28

申请号：US14524628

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L21/8238 ,  H01L21/308

CPC classification number: H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate; providing first material layers and second material layers above the substrate, the first material layers interleaved with the second material layers; removing portions of the first material layers and second material layers, the removing forming a plurality of nanowire stacks, including first material nanowires and second material nanowires; removing the first material nanowires from at least one nanowire stack; and removing the second material nanowires from at least one other nanowire stack, where the at least one nanowire stack and at least one other nanowire stack include a p-type nanowire stack(s) and a n-type nanowire stack(s), respectively.

Abstract translation: 提出了用于促进纳米线结构的制造的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括，例如：提供基底; 在所述衬底上方提供第一材料层和第二材料层，所述第一材料层与所述第二材料层交错; 去除第一材料层和第二材料层的部分，去除形成多个纳米线堆叠，包括第一材料纳米线和第二材料纳米线; 从至少一个纳米线堆叠去除所述第一材料纳米线; 以及从至少一个其它纳米线堆叠去除所述第二材料纳米线，其中所述至少一个纳米线堆叠和至少一个其它纳米线堆叠分别包括p型纳米线堆叠和n型纳米线堆叠 。