公开(公告)号：US20170271220A1

公开(公告)日：2017-09-21

申请号：US15075378

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan

IPC: H01L21/66 ,  H01L29/423 ,  H01L27/12 ,  H01L21/84 ,  H01L27/11 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L22/30 ,  H01L21/30604 ,  H01L21/823456 ,  H01L21/84 ,  H01L22/12 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/4236

Abstract: In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

公开(公告)号：US09685336B1

公开(公告)日：2017-06-20

申请号：US15055954

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Elliot John Smith

IPC: H01L21/66 ,  H01L21/28 ,  H01L21/033

CPC classification number: H01L21/28123 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/26

Abstract: A method of monitoring critical dimensions of gate electrode structures is provided including providing a substrate, forming a gate electrode pattern on the substrate comprising forming gate electrode lines parallel to each other, forming a mask layer on the gate electrode pattern and forming openings in the mask layer in a crosswise direction with respect to the direction of the parallel gate electrode lines, thereby exposing portions of the gate electrode pattern, etching exposed portions of the gate electrode pattern through the mask layer openings, thereby obtaining a negative image of the mask layer openings, removing remaining portions of the mask layer, and monitoring dimensions of the mask layer openings.

公开(公告)号：US10811433B2

公开(公告)日：2020-10-20

申请号：US16446906

申请日：2019-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/8238

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

公开(公告)号：US20200083223A1

公开(公告)日：2020-03-12

申请号：US16129221

申请日：2018-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Nigel Chan ,  Elliot John Smith

IPC: H01L27/092 ,  H03K19/0948 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/762

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

公开(公告)号：US20190312038A1

公开(公告)日：2019-10-10

申请号：US15948016

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Elliot John Smith ,  Ming-Cheng Chang

IPC: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092

Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which a contact element at the source side of a pull-down transistor in a RAM cell may connect to the back gate region in a fully depleted SOI transistor architecture. In this manner, the complexity of at least some metallization layers may be reduced, thereby providing the potential of reducing parasitic bit line capacitance. Furthermore, in some illustrative embodiments, the contact regime for connecting the back gate region to a reference potential may be omitted, thereby reducing overall floor space of respective designs.

公开(公告)号：US20190035815A1

公开(公告)日：2019-01-31

申请号：US15664061

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/266

CPC classification number: H01L27/1207 ,  H01L21/266 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/84

Abstract: A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.

公开(公告)号：US10157996B2

公开(公告)日：2018-12-18

申请号：US15648889

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

公开(公告)号：US10079605B2

公开(公告)日：2018-09-18

申请号：US15683369

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael Otto ,  Nigel Chan

IPC: H03K19/094 ,  H03K19/0948 ,  H03K19/20

CPC classification number: H03K19/09429 ,  H03K19/09487 ,  H03K19/20

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

公开(公告)号：US09793372B1

公开(公告)日：2017-10-17

申请号：US15163806

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L21/308 ,  H01L21/306 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/7831

Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.

公开(公告)号：US09490007B1

公开(公告)日：2016-11-08

申请号：US14718574

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Germain Bossu ,  Michael Otto

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L27/1108

Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

Abstract translation: 一种包括以行和列排列的多个静态随机存取存储器（SRAM）位单元的器件，其中SRAM位单元包括完全耗尽的绝缘体上的硅场效应晶体管（FDSOI-FET）。 FDSOI-FET包括P沟道上拉晶体管，其中每个P沟道上拉晶体管包括一个后栅极。 该设备还包括多个位线，其中每个位线电连接到一列的SRAM位单元和多个字线，其中每个字线电连接到其中一行的SRAM位单元。 该装置还包括位线控制电路，其被配置为选择至少一个用于写入的列，其中在写入操作期间，将第一控制信号施加到至少一个列的P沟道上拉晶体管的背栅极 选择用于写入的第二控制信号和未被选择用于写入的列的P沟道上拉晶体管的后栅极。