公开(公告)号：US20150145000A1

公开(公告)日：2015-05-28

申请号：US14092232

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Alban Zaka ,  Kun-Hsien Lin

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract translation: 提供了具有靠近浅沟槽隔离的电气部件的集成电路以及用于制造这种集成电路的方法。 该方法包括形成沟槽是衬底，其中沟槽具有沟槽表面。 包括硅和锗的阻挡层形成在沟槽表面上。 然后用覆盖阻挡层的芯形成浅沟槽隔离，其中芯包括浅沟槽隔离绝缘体。

公开(公告)号：US20150076618A1

公开(公告)日：2015-03-19

申请号：US14031361

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854

Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.

Abstract translation: 为集成电路提供了方法和装置。 该方法包括在衬底上形成波纹掩模，并在衬底上形成通道波纹。 将波纹掩模从基板上移除，并且在衬底上形成覆盖通道波纹的栅极绝缘体。 栅极形成在通道栅极绝缘体上方。

公开(公告)号：US08951877B2

公开(公告)日：2015-02-10

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US20140361385A1

公开(公告)日：2014-12-11

申请号：US13911857

申请日：2013-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ran Yan ,  Nicolas Sassiat ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/265 ,  H01L21/2658 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract translation: 在先进技术节点上形成半导体器件结构的方法和相应的半导体器件结构在低于100nm的技术节点上提供。 在一些说明性实施例中，在将栅极电介质层结构和用于形成栅极结构的多晶硅层图案化并且将源极和漏极区域注入到其中之前，至少将至少注入形成在电介质层结构上的多晶硅层中的氟注入工艺 门结构的两侧。

公开(公告)号：US08877582B2

公开(公告)日：2014-11-04

申请号：US13771294

申请日：2013-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Stefan Flachowsky ,  Nicolas Sassiat

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/7847

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract translation: 这里的一种方法包括在半导体衬底的有源区上方形成栅极结构，形成与栅极结构相邻的侧壁间隔结构，形成允许将离子注入栅电极但不进入有源区的源的/ 将形成用于晶体管的漏极区域，执行栅极离子注入工艺以在栅极电极中形成栅极离子注入区域并执行退火工艺。 一种N型晶体管，其包括邻近栅极结构定位的侧壁间隔结构，用于晶体管的多个源极/漏极区域和位于栅极电极中的栅极注入区域，其中栅极注入区域由磷，砷或 原子尺寸等于或大于磷离子浓度在5e18-5e21离子/ cm3范围内的原子尺寸的植入材料。

公开(公告)号：US20140319620A1

公开(公告)日：2014-10-30

申请号：US13874200

申请日：2013-04-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括第一晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第一功函数材料层，设置在第一功函数材料层上的第二功函数材料层，以及 设置在第二功函数材料层上的金属填充材料。 集成电路还包括第二晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第二功函件层，以及设置在第二功函数材料上的金属填充材料层 层。 此外，集成电路包括电阻器结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的金属填充材料层以及设置在金属填充材料层上的硅材料层。

公开(公告)号：US20140231907A1

公开(公告)日：2014-08-21

申请号：US13771294

申请日：2013-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Peter Javorka ,  Stefan Flachowsky ,  Nicolas Sassiat

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/7847

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract translation: 这里的一种方法包括在半导体衬底的有源区上方形成栅极结构，形成与栅极结构相邻的侧壁间隔结构，形成允许将离子注入栅电极但不进入有源区的源的/ 将形成用于晶体管的漏极区域，执行栅极离子注入工艺以在栅极电极中形成栅极离子注入区域并执行退火工艺。 一种N型晶体管，其包括邻近栅极结构定位的侧壁间隔结构，用于晶体管的多个源极/漏极区域和位于栅极电极中的栅极注入区域，其中栅极注入区域由磷，砷或 原子尺寸等于或大于磷离子浓度在5e18-5e21离子/ cm3范围内的原子尺寸的植入材料。