公开(公告)号：US20230032080A1

公开(公告)日：2023-02-02

申请号：US17388284

申请日：2021-07-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Mankyu Yang ,  Judson R. Holt ,  Jagar Singh ,  Alexander L. Martin ,  Richard F. Taylor, III

IPC: H01L29/735 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure that includes an asymmetric lateral bipolar junction transistor (BJT). The BJT includes an emitter, a base, a collector extension and a collector arranged side-by-side (i.e., laterally) across a semiconductor layer. The emitter, collector and collector extension have a first type conductivity with the collector extension having a lower conductivity level than either the emitter or the collector. The base has a second type conductivity that is different from the first type conductivity. With such a lateral configuration, the BJT can be easily integrated with CMOS devices on advanced SOI technology platforms. With such an asymmetric configuration and, particularly, given the inclusion of the collector extension but not an emitter extension, the BJT can achieve a relatively high collector-emitter breakdown voltage (Vbr-CEO) without a significant risk of leakage currents at high voltages. Also disclosed are method embodiments for forming such a semiconductor structure.

公开(公告)号：US11127818B2

公开(公告)日：2021-09-21

申请号：US16526529

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Srikanth Balaji Samavedam

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088

Abstract: An illustrative device includes a transistor including a first set of fins defined above a substrate, a second set of fins defined above the substrate, and a gate structure embedded in the substrate between the first set of fins and the second set of fins, wherein the first set of fins and the second set of fins are doped with a first dopant type and the substrate is doped with a second dopant type different than the first dopant type.

公开(公告)号：US20210242335A1

公开(公告)日：2021-08-05

申请号：US16776930

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Alexander L. Martin ,  Alexander M. Derrickson

IPC: H01L29/735 ,  H01L21/285 ,  H01L29/10 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L21/265 ,  H01L29/45 ,  H01L21/3065

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

公开(公告)号：US20240047555A1

公开(公告)日：2024-02-08

申请号：US17816799

申请日：2022-08-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anton V. Tokranov ,  Saloni Chaurasia ,  Hong Yu ,  Jagar Singh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823468

Abstract: A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.

公开(公告)号：US11837460B2

公开(公告)日：2023-12-05

申请号：US17550835

申请日：2021-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Alexander M. Derrickson ,  Alexander Martin

IPC: H01L29/735 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/456

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region composed of semiconductor material; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and an extrinsic base contact wrapping around the semiconductor material of the extrinsic base region.

公开(公告)号：US20230307539A1

公开(公告)日：2023-09-28

申请号：US17701751

申请日：2022-03-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jagar Singh

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66681

Abstract: A structure has a substrate, a drift region within the substrate, a semiconductor-on-insulator structure on the substrate adjacent to the drift region, a gate insulator layer having a first portion on the substrate and a second portion extending over the semiconductor-on-insulator structure, a gate conductor on the first portion, and a field plate on the gate conductor and the second portion.

公开(公告)号：US11710771B2

公开(公告)日：2023-07-25

申请号：US17524043

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Judson R. Holt ,  Haiting Wang ,  Jagar Singh ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/1008 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/6656 ,  H01L29/66242 ,  H01L29/66553 ,  H01L29/735 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

公开(公告)号：US20230084007A1

公开(公告)日：2023-03-16

申请号：US17574785

申请日：2022-01-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Jagar Singh ,  Judson Holt

IPC: H01L29/737 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.

公开(公告)号：US20230065785A1

公开(公告)日：2023-03-02

申请号：US17555561

申请日：2021-12-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jagar Singh ,  Alexander M. Derrickson ,  Alvin J. Joseph ,  Andreas Knorr ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

公开(公告)号：US11456384B2

公开(公告)日：2022-09-27

申请号：US16921068

申请日：2020-07-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Wang Zheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49

Abstract: A structure includes a semiconductor fin; a first source/drain region and a second source/drain region in the semiconductor fin; a first doping region about the first source/drain region, defining a channel region in the semiconductor fin; and a second doping region about the second source/drain region, defining a drain extension in the semiconductor fin. A gate structure is over the channel region and the drain extension. The gate structure includes a gate dielectric layer, a first metal layer adjacent a second metal layer over the gate dielectric layer, and a contiguous gate conductor over the first metal layer and the second metal layer. One of the metal layers is over the channel region and the other is over the drain extension. The metal layers may have different thicknesses and/or work functions, to improve transconductance and RF performance of an LDMOS FinFET including the structure.