TRANSISTOR WITH MULTI-LEVEL SELF-ALIGNED GATE AND SOURCE/DRAIN TERMINALS AND METHODS

    公开(公告)号:US20220223694A1

    公开(公告)日:2022-07-14

    申请号:US17146513

    申请日:2021-01-12

    Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

    FIELD EFFECT TRANSISTOR WITH BURIED FLUID-BASED GATE AND METHOD

    公开(公告)号:US20230324332A1

    公开(公告)日:2023-10-12

    申请号:US17715282

    申请日:2022-04-07

    CPC classification number: G01N27/4148 G01N27/4145

    Abstract: Disclosed is a semiconductor structure including a device (e.g., a field effect transistor (FET), a biosensor FET (bioFET) or an ion-sensitive FET (ISFET)) with a fluid-based gate. The structure includes a substrate, an intermediate layer on the substrate, and a semiconductor layer on the intermediate layer. The device includes, within the semiconductor layer, a source region, a drain region, and a channel region between the source and drain regions. The structure includes, for the fluid-base gate, a cavity within the intermediate layer below the channel region and lined with a dielectric liner. Optionally, the exposed surface of the dielectric liner within the cavity is functionalized. Additional dielectric layers are stacked on the semiconductor layer and at least one port extends essentially vertically through the dielectric layers, the semiconductor layer and the dielectric liner to the cavity so as to allow fluid for the fluid-based gate to flow into the cavity.

    Waveguide with attenuator
    29.
    发明授权

    公开(公告)号:US11422303B2

    公开(公告)日:2022-08-23

    申请号:US17108732

    申请日:2020-12-01

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a waveguide structure with attenuator and methods of manufacture. The structure includes: a waveguide structure including semiconductor material; an attenuator underneath the waveguide structure; an airgap structure vertically aligned with and underneath the waveguide structure and the attenuator; and shallow trench isolation structures on sides of the waveguide structure and merging with the airgap structure.

    PHOTODETECTOR ARRAY WITH DIFFRACTION GRATINGS HAVING DIFFERENT PITCHES

    公开(公告)号:US20220155535A1

    公开(公告)日:2022-05-19

    申请号:US17099834

    申请日:2020-11-17

    Abstract: A photodetector array includes a substrate, and an array of pixels over the substrate. Each pixel includes a set of diffraction gratings directly on a semiconductor photodetector. A pitch of the set of diffraction gratings associated with each pixel in the array of pixels are different to enable each pixel to detect a specific wavelength of light different than other pixels of the array of pixels. An air cavity may be provided in the substrate under the germanium photodetector to improve light absorption. A method of forming the photodetector array is also disclosed.

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