公开(公告)号：US10964796B2

公开(公告)日：2021-03-30

申请号：US15427182

申请日：2017-02-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/737 ,  H01L21/762 ,  H01L29/732

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the base region.

公开(公告)号：US10923427B2

公开(公告)日：2021-02-16

申请号：US16266196

申请日：2019-02-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/762 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US12243923B2

公开(公告)日：2025-03-04

申请号：US17506992

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N. R. Vanukuru ,  Mark Levy

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

公开(公告)号：US12027580B2

公开(公告)日：2024-07-02

申请号：US17028178

申请日：2020-09-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Siva P. Adusumilli ,  Bruce W. Porth ,  John J. Ellis-Monaghan

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/02505 ,  H01L21/7624 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor on insulator substrate with cavity structures and methods of manufacture. The structure includes: a bulk substrate with at least one rectilinear cavity structure; an insulator material sealing the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and over the at least one rectilinear cavity structure.

公开(公告)号：US20230096544A1

公开(公告)日：2023-03-30

申请号：US17449336

申请日：2021-09-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L21/763

Abstract: A transistor includes a bulk semiconductor substrate, and first and second raised source/drain regions above the bulk semiconductor substrate. A gate is between the first and second raised source/drain regions. A first dielectric section is beneath the first raised source/drain region in the bulk semiconductor substrate, and a second dielectric section is beneath the second raised source/drain region in the bulk semiconductor substrate. A first air gap is defined in at least the first dielectric section under the first raised source/drain region, and a second air gap is defined in at least the second dielectric section under the second raised source/drain region. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

公开(公告)号：US11605710B2

公开(公告)日：2023-03-14

申请号：US17155469

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma B. Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Srikanth Srihari

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L29/10

Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

公开(公告)号：US11488980B2

公开(公告)日：2022-11-01

申请号：US17003179

申请日：2020-08-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Bruce W. Porth ,  John J. Ellis-Monaghan

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with localized cavity structures and methods of manufacture. A structure includes a bulk substrate with localized semiconductor on insulator (SOI) regions and bulk device regions, the localized SOI regions includes multiple cavity structures and substrate material of the bulk substrate.

公开(公告)号：US11488950B2

公开(公告)日：2022-11-01

申请号：US17173611

申请日：2021-02-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma B. Rana ,  Vibhor Jain ,  Anthony K. Stamper ,  Qizhi Liu ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L29/732 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73

Abstract: Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate.

公开(公告)号：US11410872B2

公开(公告)日：2022-08-09

申请号：US16206375

申请日：2018-11-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L29/51 ,  H01L21/762 ,  H01L21/308 ,  H01L29/10 ,  H01L21/306 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.

公开(公告)号：US11380759B2

公开(公告)日：2022-07-05

申请号：US16939213

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Johnatan A. Kantarovsky ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/763 ,  H01L21/8234 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.