公开(公告)号：US5448743A

公开(公告)日：1995-09-05

申请号：US917497

申请日：1992-07-21

申请人： Dale E. Gulick ,  Joe W. Peterson ,  Munehiro Yoshikawa ,  Hiroshi Matsubara ,  Toshihiro Fujita ,  Kazushige Tsurumi

发明人： Dale E. Gulick ,  Joe W. Peterson ,  Munehiro Yoshikawa ,  Hiroshi Matsubara ,  Toshihiro Fujita ,  Kazushige Tsurumi

IPC分类号： G06F15/78 ,  G06F13/24 ,  G06F9/46

CPC分类号： G06F13/24

摘要： An I/O port interrupt mechanism includes a source register connected to the port for reporting sources of interrupts arising within the port, an interrupt mask register connected to the source register and operable to configure the I/O port for generation of interrupts, and an interrupt controller connected to the output of the source register and operable to hold off interrupts arising within the I/O port.

摘要翻译： I / O端口中断机制包括连接到端口的源寄存器，用于报告在端口内产生的中断源，中断屏蔽寄存器连接到源寄存器，并可用于配置I / O端口以产生中断，以及 中断控制器连接到源寄存器的输出，可用于阻止I / O端口内产生的中断。

公开(公告)号：US5220601A

公开(公告)日：1993-06-15

申请号：US589065

申请日：1990-09-27

申请人： Dale E. Gulick ,  Alan R. Hendrickson

发明人： Dale E. Gulick ,  Alan R. Hendrickson

IPC分类号： G06F3/02 ,  G06F3/023 ,  H03M11/22 ,  H04M1/26

CPC分类号： H03M11/22 ,  G06F3/021 ,  G06F3/023 ,  H04M1/26

摘要： A keypad status reporting system provides an indication over a serial bus as to which switch of a plurality of keypad switches is being selected by an operator wherein each keypad switch is coupled between a respective different pair of row and column conductors. The system generates parallel three-bit row and column addresses, combines the row and column addresses to form a parallel six-bit key code, and converts the key code to serial bits of data and places the serial bits of data onto a multiplexed bus in a predetermined channel.

公开(公告)号：US07421525B2

公开(公告)日：2008-09-02

申请号：US10842296

申请日：2004-05-10

申请人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

发明人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/00 ,  G11C5/06

CPC分类号： G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

摘要翻译： 一种系统，包括耦合到串行连接的存储器模块链的主机。 在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控​​制集线器。 存储器模块通过多个存储器链路串联地连接到主机。 每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。 上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。 存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

公开(公告)号：US20080178181A1

公开(公告)日：2008-07-24

申请号：US11924146

申请日：2007-10-25

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F9/46

CPC分类号： G06F11/0715 ,  G06F9/4812 ,  G06F9/485 ,  G06F11/0757

摘要： A method and apparatus is provided for processing tasks with failure recovery. The method includes storing one or more tasks in a queue, wherein each task has an associated exit routine, and determining at least one task to process based on a priority scheme. The method further includes processing the at least one task, and calling the exit routine based on determining that the task has not completed processing within a preselected period of time.

摘要翻译： 提供了一种用于处理具有故障恢复的任务的方法和装置。 该方法包括将一个或多个任务存储在队列中，其中每个任务具有关联的退出例程，以及基于优先级方案确定至少一个任务进行处理。 所述方法还包括处理所述至少一个任务，并且基于确定所述任务尚未在预选的时间段内完成处理来调用所述退出例程。

公开(公告)号：US07308514B1

公开(公告)日：2007-12-11

申请号：US10647397

申请日：2003-08-25

申请人： Larry D. Hewitt ,  Dale E. Gulick

发明人： Larry D. Hewitt ,  Dale E. Gulick

IPC分类号： G06F13/38

CPC分类号： G06F13/4027

摘要： Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

摘要翻译： 计算机系统配置资源包括在第一和第二集成电路中的第一和第二控制电路。 通过多个逻辑管道传送数据的通信链路连接两个集成电路。 链路的配置使用包括第一控制电路内的上游（位于最靠近CPU）的配置寄存器和第二控制电路（（位于距离CPU最远）配置寄存器）的链路桥接器，链路头 包括用于第一控制电路的上行数据和第二控制电路的下行数据用于初始化链路，上游和下行数据可以包括指定通信链路大小的信息。

公开(公告)号：US07127573B1

公开(公告)日：2006-10-24

申请号：US09564765

申请日：2000-05-04

申请人： Geoffrey S. S. Strongin ,  Brian D. McMinn ,  Dale E. Gulick

发明人： Geoffrey S. S. Strongin ,  Brian D. McMinn ,  Dale E. Gulick

IPC分类号： G06F12/06

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F12/0215 ,  G06F13/1626 ,  G06F13/1694 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory controller includes a power mode sensitive reordering device coupled to receive a power mode indication. The memory controller includes a selectable high and low power mode. An indication of which of the high and low power modes is selected is coupled to the power mode sensitive reordering device as the power mode indication. In the low power mode, memory transactions are reordered to minimize power consumption in memory devices controlled by the memory controller.

摘要翻译： 存储器控制器包括耦合以接收功率模式指示的功率模式敏感重新排序装置。 存储器控制器包括可选择的高和低功率模式。 选择高功率模式和低功率模式中的哪一种的指示作为功率模式指示耦合到功率模式敏感重新排序装置。 在低功耗模式下，存储器事务被重新排序以最小化由存储器控制器控制的存储器件中的功耗。

公开(公告)号：US07065654B1

公开(公告)日：2006-06-20

申请号：US09852372

申请日：2001-05-10

申请人： Dale E. Gulick ,  Geoffrey S. Strongin

发明人： Dale E. Gulick ,  Geoffrey S. Strongin

IPC分类号： H04L9/00

CPC分类号： G06F21/85 ,  G06F21/72

摘要： A system and method for secure computing. The system includes a processor, one or more secured assets coupled to the processor, and security hardware. The processor is configured to operate in various operating modes, including a secure operating mode. The security hardware is configured to control access to the secured assets dependant upon the operating mode of the processor. The security hardware is configured to allow access to the secure assets in the secure operating mode, preferably only in the secure operating mode. The method includes switching the computer system between operating modes, while allowing or restricting access to the secured assets based on the operating modes. The second operating mode comprises a secure operating mode. The method restricts access to the secured assets in the first operating mode and permits access to the secured assets in the secure operating mode.

摘要翻译： 一种用于安全计算的系统和方法。 该系统包括处理器，耦合到处理器的一个或多个安全资产以及安全硬件。 处理器被配置为在各种操作模式下操作，包括安全操作模式。 安全硬件被配置为根据处理器的操作模式控制对安全资产的访问。 安全硬件被配置为允许以安全操作模式访问安全资产，优选仅在安全操作模式下。 该方法包括在操作模式之间切换计算机系统，同时基于操作模式允许或限制对安全资产的访问。 第二操作模式包括安全操作模式。 该方法限制了在第一操作模式下对安全资产的访问，并允许以安全操作模式访问安全资产。

公开(公告)号：US06968460B1

公开(公告)日：2005-11-22

申请号：US09854040

申请日：2001-05-11

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F7/58 ,  G06F21/00

CPC分类号： G06F21/6227 ,  G06F7/58 ,  G06F21/78

摘要： A random number generator and method thereto using an entropy register. The method includes providing a first plurality of bit entries in an entropy register and transmitting a bit value from each of a plurality of registers to one of the first plurality of bit entries in the entropy register. The random number generator comprises an entropy register configured to receive bits over a plurality of data lines that each couple to an individual entry in the entropy register. The random number generator may further include an entropy control unit configured to provide a value from the entropy register in response to a request for a random number.

摘要翻译： 一种随机数发生器及其使用熵寄存器的方法。 该方法包括在熵寄存器中提供第一多个比特条目，并将多个寄存器中的每一个的比特值发送到熵寄存器中的第一多个比特条目之一。 随机数生成器包括熵寄存器，其被配置为在多个数据线上接收位，每个数据线耦合到熵寄存器中的单个条目。 随机数生成器还可以包括熵控制单元，其被配置为响应于对随机数的请求从熵寄存器提供值。

公开(公告)号：US06651128B1

公开(公告)日：2003-11-18

申请号：US09501889

申请日：2000-02-10

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1300

CPC分类号： G06F13/362

摘要： Several different systems and methods are described involving arbitration between asynchronous and isochronous data for access to a data transport resource (e.g., a bus or a memory controller). A first embodiment of a system (e.g., a computer system or a communication system) includes an arbiter coupled to the data transport resource, an asynchronous queue for storing asynchronous data, and an isochronous queue for storing isochronous data. The isochronous queue has a data level range divided into multiple portions. A number of memory locations within the isochronous queue may define the data level range of the isochronous queue. The arbiter arbitrates between the asynchronous queue and the isochronous queue for access to the data transport resource dependent upon the portion of the data level range in which a level of data resides within the isochronous queue. The level of data within the isochronous queue may be a number of memory locations between a write pointer and a read pointer. The arbiter may include a set of arbitration rules, wherein each arbitration rule states conditions used to determine whether data is provided from the isochronous queue or the asynchronous queue. The arbiter may arbitrate between the asynchronous queue and the isochronous queue for access to the data transport resource by: (i) selecting an arbitration rule from the set of arbitration rules dependent upon the portion of the data level range in which the level of data resides within the isochronous queue, and (ii) applying the rule.

摘要翻译： 描述了涉及用于访问数据传输资源（例如，总线或存储器控制器）的异步和同步数据之间的仲裁的若干不同的系统和方法。 系统（例如，计算机系统或通信系统）的第一实施例包括耦合到数据传输资源的仲裁器，用于存储异步数据的异步队列和用于存储等时数据的等时队列。 同步队列具有分为多个部分的数据级别范围。 同步队列内的多个存储器位置可以定义等时队列的数据级别范围。 仲裁器在异步队列和同步队列之间进行仲裁，用于访问数据传输资源，这取决于数据级别的数据级别驻留在同步队列中的部分。 同步队列内的数据级别可以是写指针和读指针之间的多个存储器位置。 仲裁器可以包括一组仲裁规则，其中每个仲裁规则说明用于确定数据是否从等时队列或异步队列提供的条件。 仲裁器可以通过以下方式在异步队列和等时队列之间进行仲裁以访问数据传输资源：（i）根据数据级别所在的数据级别范围的部分从仲裁规则集中选择仲裁规则 在同步队列内，以及（ii）应用规则。

公开(公告)号：US06625743B1

公开(公告)日：2003-09-23

申请号：US09933290

申请日：2001-08-20

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F112

CPC分类号： G06F1/12 ,  G06F13/4217

摘要： A method of synchronizing the generation and consumption of isochronous data in a computer system. In one embodiment, a computer system implements a method comprising providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data, outputting a master clock signal to the plurality of isochronous sinks or sources, synchronizing said clocks to said master clock signal so that the generation or consumption of the isochronous data is synchronized to said master clock signal, outputting said master clock signal to an interrupt controller, and generating an interrupt based on said master clock signal, wherein a processor schedules one or more tasks that generate or consume data based on said interrupt. The isochronous sinks or sources may also be synched to a multiple of the master clock signal.

摘要翻译： 一种在计算机系统中同步同步数据的生成和消耗的方法。 在一个实施例中，计算机系统实现一种方法，包括向被配置为产生或消耗同步数据的多个同步宿或源提供多个时钟，将主时钟信号输出到多个同步宿或源，同步所述时钟 到所述主时钟信号，使得同步数据的产生或消耗与所述主时钟信号同步，将所述主时钟信号输出到中断控制器，并且基于所述主时钟信号产生中断，其中处理器调度一个或 基于所述中断产生或消耗数据的更多任务。 同步吸收器或源也可以被同步到主时钟信号的倍数。