公开(公告)号：US20150126028A1

公开(公告)日：2015-05-07

申请号：US14071070

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES, Inc

Inventor： Errol Todd Ryan ,  Kunaljeet Tanwar ,  Xunyuan Zhang

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有包括元素金属材料的第一暴露表面和包括阻挡材料的第二暴露表面的半导体衬底。 当暴露于湿蚀刻剂时，元素金属材料具有第一蚀刻速率，并且当暴露于湿蚀刻剂时，阻挡材料具有第二蚀刻速率。 此外，该方法包括修改第一暴露表面以形成修饰的第一暴露表面，以便当暴露于湿蚀刻剂时降低第一蚀刻速率，并将湿蚀刻剂同时施加到修饰的第一暴露表面和第二暴露表面。

公开(公告)号：US08889549B2

公开(公告)日：2014-11-18

申请号：US13766898

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L2221/1063

Abstract: One illustrative method disclosed herein includes performing a first etching process to define a via opening in a layer of insulating material, performing at least one process operation to form a sacrificial liner layer on the sidewalls of the via opening, performing a second etching process to define a trench in the layer of insulating material, wherein the sacrificial liner layer is exposed to the second etching process, after performing the second etching process, performing a third etching process to remove the sacrificial liner layer and, after performing the third etching process, forming a conductive structure in at least the via opening and the trench.

Abstract translation: 本文公开的一种说明性方法包括执行第一蚀刻工艺以在绝缘材料层中限定通孔开口，执行至少一个工艺操作以在通孔开口的侧壁上形成牺牲衬垫层，执行第二蚀刻工艺以界定 在所述绝缘材料层中的沟槽，其中所述牺牲衬垫层在进行所述第二蚀刻工艺之后暴露于所述第二蚀刻工艺，执行第三蚀刻工艺以去除所述牺牲衬垫层，并且在执行所述第三蚀刻工艺之后，形成 至少在通孔开口和沟槽中的导电结构。

公开(公告)号：US20140327140A1

公开(公告)日：2014-11-06

申请号：US13887174

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括提供在其中和/或其上设置有器件的半导体衬底。 包括阻挡层和覆盖阻挡层的插塞金属的接触结构形成为与器件电接触。 覆盖接触结构的硬掩模形成。 该方法包括执行蚀刻以形成通过硬掩模的通孔，并暴露阻挡层和插塞金属。 此外，该方法用湿蚀刻剂去除硬掩模的剩余部分，而接触结构被配置为抑制湿蚀刻剂蚀刻阻挡层。 在该方法中，通孔开口填充有导电材料以形成与接触结构的互连。

公开(公告)号：US20140217588A1

公开(公告)日：2014-08-07

申请号：US13757338

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

公开(公告)号：US20140210088A1

公开(公告)日：2014-07-31

申请号：US14227807

申请日：2014-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

IPC: H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy.

Abstract translation: 半导体器件包括限定在电介质层中的凹部，凹部具有延伸到凹部的上角部的上侧壁部分和在上侧壁部分下方的下侧壁部分。 互连结构定位在凹槽中。 互连结构包括连续的衬垫层，其具有分别位于上下侧壁部分的横向相邻的上层和下层部分。 上层部分包括第一过渡金属和第二过渡金属的合金，下层部分包括第二过渡金属，但不包括第一过渡金属。 互连结构还包括基本上填充凹部的填充材料，其中第二过渡金属对于填充材料具有比合金更高的润湿性。

公开(公告)号：US08704372B2

公开(公告)日：2014-04-22

申请号：US13849415

申请日：2013-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol T. Ryan ,  Xunyuan Zhang

IPC: H01L23/48

CPC classification number: H01L23/535 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.

Abstract translation: 提供集成电路，用于凹入衬底内的嵌入式铜特征的工艺，以及用于使集成电路的层间电介质衬底内的嵌入式铜互连凹陷的工艺。 在一个实施例中，在诸如层间电介质基板的衬底内嵌入诸如嵌入式铜互连的嵌入式铜特征的方法包括提供其中布置有嵌入式铜特征的衬底。 嵌入的铜特征具有暴露的表面，并且衬底具有与嵌入的铜特征的暴露表面相邻的衬底表面。 嵌入的铜特征的暴露表面被氮化以在嵌入的铜特征中形成一层氮化铜。 从嵌入的铜特征中选择性地蚀刻氮化铜以将嵌入的铜特征凹入到衬底内。

公开(公告)号：US10573593B2

公开(公告)日：2020-02-25

申请号：US15983168

申请日：2018-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Shao Beng Law ,  James Jay McMahon

IPC: H01L21/4763 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

公开(公告)号：US10366919B2

公开(公告)日：2019-07-30

申请号：US15709956

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. Licausi ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3213

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

公开(公告)号：US20190221473A1

公开(公告)日：2019-07-18

申请号：US16364465

申请日：2019-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76813 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

公开(公告)号：US20190206718A1

公开(公告)日：2019-07-04

申请号：US15860121

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Shao Beng Law ,  Sunil K. Singh ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/31058 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76828 ,  H01L23/528 ,  H01L23/53295 ,  H01L2221/1047

Abstract: Interconnect structures and methods for forming an interconnect structure. First and second metallization structures are formed in an intralayer dielectric layer. The intralayer dielectric layer is removed to form a cavity with an entrance between the first and second metallization structures. A dielectric layer is deposited on surfaces surrounding the cavity, over the first metallization structure, and over the second metallization structure. A sacrificial material is formed inside the cavity after the dielectric layer is deposited. A cap layer is deposited on the dielectric layer over the first metallization structure, the dielectric layer over the second metallization structure, and the sacrificial material inside the cavity to close the entrance to the cavity. After the cap layer is deposited, the sacrificial material is removed from the cavity. The dielectric layer and cap layer cooperate to encapsulate an air gap inside the cavity.