公开(公告)号：US11610965B2

公开(公告)日：2023-03-21

申请号：US17185236

申请日：2021-02-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Hui Zang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/764 ,  H01L21/768

Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.

公开(公告)号：US11121023B2

公开(公告)日：2021-09-14

申请号：US16548192

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Hong Yu ,  Jinping Liu ,  Hui Zang

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A finFET device is disclosed including a fin defined in a semiconductor substrate, the fin having an upper surface and a first diffusion break positioned in the fin, wherein the first diffusion break comprises an upper surface that is substantially coplanar with the upper surface of the fin.

公开(公告)号：US11094827B2

公开(公告)日：2021-08-17

申请号：US16434136

申请日：2019-06-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yanping Shen ,  Xiaoxiao Zhang ,  Shesh Mani Pandey ,  Hui Zang

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49

Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component.

公开(公告)号：US20210183997A1

公开(公告)日：2021-06-17

申请号：US17185236

申请日：2021-02-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Hui Zang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/764 ,  H01L21/768

Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.

公开(公告)号：US20210151451A1

公开(公告)日：2021-05-20

申请号：US16683439

申请日：2019-11-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Shesh Mani Pandey

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/423

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.

公开(公告)号：US11011604B2

公开(公告)日：2021-05-18

申请号：US16437440

申请日：2019-06-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

Abstract: A device includes a first gate structure positioned above an active region defined in a semiconducting substrate. A first spacer is positioned adjacent the first gate structure. First conductive source/drain contact structures are positioned adjacent the first gate structure and separated from the first gate structure by the first spacer. A first recessed portion of the first conductive source/drain contact structures is positioned at a first axial position along the first gate structure. A second recessed portion of the first conductive source/drain contact structures is positioned at a second axial position along the gate structure. A dielectric cap layer is positioned above the first and second recessed portions. A first conductive contact contacts the first gate structure in the first axial position. The dielectric cap layer above the first recessed portion is positioned adjacent the first conductive contact.

公开(公告)号：US10957578B2

公开(公告)日：2021-03-23

申请号：US16146413

申请日：2018-09-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Wei Hong ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu ,  Liu Jiang

IPC: H01L21/762 ,  H01L27/12 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.

公开(公告)号：US10923469B2

公开(公告)日：2021-02-16

申请号：US16244169

申请日：2019-01-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hui Zang ,  Guowei Xu ,  Jiehui Shu ,  Ruilong Xie ,  Yurong Wen ,  Garo J. Derderian ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L27/06 ,  H01L29/66 ,  H01L49/02 ,  H01L21/762 ,  H01L23/522 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.