公开(公告)号：US06440793B1

公开(公告)日：2002-08-27

申请号：US09757514

申请日：2001-01-10

申请人： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

发明人： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

IPC分类号： H01L218242

CPC分类号： H01L27/10841 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

公开(公告)号：US06355520B1

公开(公告)日：2002-03-12

申请号：US09374537

申请日：1999-08-16

申请人： Youngjin Park ,  Heon Lee

发明人： Youngjin Park ,  Heon Lee

IPC分类号： H01L21336

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876

摘要： In accordance with the present invention, a method for forming gate conductors in 4F2 area stacked capacitor memory cells includes the steps of forming a buried bit line in a substrate, forming an active area above and in contact with the buried bit line and separating portions of the active area by forming a dielectric material in trenches around the portions of the active area. Portions of the dielectric material are removed adjacent to and selective to the portions of the active area. A first portion of a gate conductor is formed in locations from which the portion of dielectric material is removed, and a second portion of the gate conductor is formed on a top surface of the dielectric material and in contact with the first portion of the gate conductor. Stacked capacitors are formed such that the gate conductor activates an access transistor formed in the portions of the active area. A layout is also included.

摘要翻译： 根据本发明，一种在4F2区域层叠电容器存储单元中形成栅极导体的方法包括以下步骤：在衬底中形成掩埋位线，在掩埋位线上方形成有源区，并与掩埋位线接触并分离部分 有源区域通过在有源区域的部分周围的沟槽中形成电介质材料。 电介质材料的一部分被移除并且与有源区的部分有选择性地去除。 栅极导体的第一部分形成在绝缘材料部分被去除的位置，并且栅极导体的第二部分形成在电介质材料的顶表面上并与栅极导体的第一部分接触 。 堆叠的电容器形成为使得栅极导体激活形成在有源区域的部分中的存取晶体管。 还包括布局。

公开(公告)号：US06294436B1

公开(公告)日：2001-09-25

申请号：US09374538

申请日：1999-08-16

申请人： Youngjin Park ,  Heon Lee

发明人： Youngjin Park ,  Heon Lee

IPC分类号： H01L2120

CPC分类号： H01L27/10852

摘要： In accordance with the present invention, a method for expanding holes for the formation of stacked capacitors is described and claimed. The method includes the steps of providing a planarized dielectric layer for forming bottom electrodes of the stacked capacitors, forming a first dielectric layer on the planarized dielectric layer, forming a second dielectric layer on the first dielectric layer. The second dielectric layer is selectively etchable relative to the first dielectric layer. The steps of etching the second dielectric layer to form holes for forming the bottom electrodes and isotropically etching the second dielectric layer to expand the holes for forming the bottom electrodes are also included.

摘要翻译： 根据本发明，描述并要求保护用于形成叠层电容器的孔的方法。 该方法包括以下步骤：提供用于形成层叠电容器的底部电极的平坦化介电层，在平坦化电介质层上形成第一电介质层，在第一电介质层上形成第二电介质层。 第二电介质层相对于第一介电层可选择性地蚀刻。 还包括蚀刻第二电介质层以形成用于形成底部电极的孔和各向同性蚀刻第二电介质层以扩大用于形成底部电极的孔的步骤。

公开(公告)号：US20060086986A1

公开(公告)日：2006-04-27

申请号：US11255458

申请日：2005-10-20

申请人： Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Szepesi ,  Heon Lee

发明人： Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Szepesi ,  Heon Lee

IPC分类号： H01L29/76

CPC分类号： B82Y10/00 ,  G11B9/08 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/1436 ,  G11B11/08

摘要： A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting layer and a conductive gate, wherein the conductive gate and the charge trapping structure move relative to the other, wherein an electric field applied across the second semiconducting layer and the conductive gate traps charge in the charge trapping structure.

公开(公告)号：US20050176206A1

公开(公告)日：2005-08-11

申请号：US11104997

申请日：2005-04-13

申请人： Manish Sharma ,  Thomas Anthony ,  Heon Lee

发明人： Manish Sharma ,  Thomas Anthony ,  Heon Lee

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L43/12

CPC分类号： H01L43/12

摘要： An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil depositing a dielectric material, planarizing the dielectric material thereby exposing a portion of the at least one material and depositing a conductor material in contact with the exposed portion of the at least one material.

摘要翻译： 本发明的一个方面是在薄膜器件中形成接触的方法。 该方法包括形成剥离模板，通过提升模板沉积至少一种材料，去除沉积介电材料的剥离模板的一部分，平坦化介电材料，从而暴露至少一种材料的一部分并将导体材料沉积在 与所述至少一种材料的暴露部分接触。

公开(公告)号：US20050170628A1

公开(公告)日：2005-08-04

申请号：US10770083

申请日：2004-01-31

申请人： Manish Sharma ,  Thomas Anthony ,  Heon Lee

发明人： Manish Sharma ,  Thomas Anthony ,  Heon Lee

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/44 ,  H01L43/12

CPC分类号： H01L21/0331 ,  H01L21/0272 ,  H01L21/31144 ,  H01L43/12 ,  Y10S438/951

摘要： An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, forming a re-entrant profile with the remaining portion of the liftoff stencil and depositing a conductor material in contact with the at least one material on the re-entrant profile.

摘要翻译： 本发明的一个方面是在薄膜器件中形成接触的方法。 该方法包括形成剥离模板，将至少一种材料沉积通过剥离模板，去除剥离模板的一部分，与剥离模板的剩余部分形成重新进入的模型并且沉积导体材料与所述脱模模板接触。 至少一个材料在入口轮廓。

公开(公告)号：US20050088174A1

公开(公告)日：2005-04-28

申请号：US10692694

申请日：2003-10-27

申请人： Seung Lee ,  Heon Lee ,  Byung Oh

发明人： Seung Lee ,  Heon Lee ,  Byung Oh

IPC分类号： G01R33/035 ,  G01R33/02

CPC分类号： G01R33/0356

摘要： Disclosed a SQUID (Superconducting QUantum Interference Device) sensor using an auxiliary sensor, including: a SQUID sensing unit having a SQUID and a first feedback coil for creating a magnetic field at a periphery of the SQUID; an auxiliary sensor having a lower magnetic sensitivity and a higher operation range than the SQUID sensing unit; and a sensor reading unit for operating the SQUID sensing unit and the auxiliary sensor to read out a signal of the SQUID and at the same time, supplying the SQUID sensing unit with an offset magnetic field through the first feedback coil.

摘要翻译： 公开了一种使用辅助传感器的SQUID（超导量子干涉仪）传感器，包括：具有SQUID的SQUID感测单元和用于在SQUID的周边产生磁场的第一反馈线圈; 辅助传感器，其具有比SQUID感测单元更低的灵敏度和更高的操作范围; 以及传感器读取单元，用于操作SQUID感测单元和辅助传感器以读出SQUID的信号，并且同时向SQUID感测单元提供穿过第一反馈线圈的偏移磁场。

公开(公告)号：US06326260B1

公开(公告)日：2001-12-04

申请号：US09599703

申请日：2000-06-22

申请人： Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

发明人： Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823462 ,  H01L27/10873

摘要： A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.

摘要翻译： 提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。 具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层 形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层 所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及 所述多晶硅层在所述导体材料层上形成氮化物覆盖层 形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。

公开(公告)号：US06284666B1

公开(公告)日：2001-09-04

申请号：US09583963

申请日：2000-05-31

申请人： Munir D. Naeem ,  Gangadhara S. Mathad ,  Byeong Yeol Kim ,  Stephan P. Kudelka ,  Brian S. Lee ,  Heon Lee ,  Elizabeth Morales ,  Young-Jin Park ,  Rajiv M. Ranade

发明人： Munir D. Naeem ,  Gangadhara S. Mathad ,  Byeong Yeol Kim ,  Stephan P. Kudelka ,  Brian S. Lee ,  Heon Lee ,  Elizabeth Morales ,  Young-Jin Park ,  Rajiv M. Ranade

IPC分类号： H01L21302

CPC分类号： H01L21/3081 ,  H01L21/3065

摘要： A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e.,

摘要翻译： 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， <30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度。

公开(公告)号：US07709882B2

公开(公告)日：2010-05-04

申请号：US11255458

申请日：2005-10-20

申请人： Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Louis Szepesi, Jr. ,  Heon Lee

发明人： Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Louis Szepesi, Jr. ,  Heon Lee

IPC分类号： H01L29/788

CPC分类号： B82Y10/00 ,  G11B9/08 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/1436 ,  G11B11/08

摘要： A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting layer and a conductive gate, wherein the conductive gate and the charge trapping structure move relative to the other, wherein an electric field applied across the second semiconducting layer and the conductive gate traps charge in the charge trapping structure.

摘要翻译： 存储装置包括具有p-掺杂剂的第一半导体层和具有n-掺杂剂的第二半导体层，其设置在第一半导体层上，形成第一和第二半导体层之间的结。 存储装置还包括设置在第二半导体层上的电荷捕获结构和导电栅极，其中导电栅极和电荷捕获结构相对于另一个迁移，其中施加在第二半导体层和导电栅极阱上的电场 电荷捕获结构中的电荷。