公开(公告)号：US20110207317A1

公开(公告)日：2011-08-25

申请号：US13053733

申请日：2011-03-22

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L21/768

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US07872314B2

公开(公告)日：2011-01-18

申请号：US12727334

申请日：2010-03-19

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L23/62

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US07696050B2

公开(公告)日：2010-04-13

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US5534458A

公开(公告)日：1996-07-09

申请号：US442925

申请日：1995-05-17

申请人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/04 ,  H01L27/105 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/3205 ,  H01L28/40 ,  H01L28/55 ,  Y10S257/915 ,  Y10S438/978

摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

公开(公告)号：US5459345A

公开(公告)日：1995-10-17

申请号：US264092

申请日：1994-06-22

申请人： Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/00

CPC分类号： H01L27/10852

摘要： An object of the invention is to provide a semiconductor device which has a capacitor having good anti-leak characteristics and good breakdown voltage characteristics and is suitable to high integration. Source/drain regions (25) are formed at a surface of a silicon substrate (31). Interlayer insulating films (1) and (3) having contact holes (1a) and (3a), through which a surfaces of the source/drain region is partially exposed, is formed on the surface of silicon substrate (31). Contact holes (1a) and (3a) are filled with plug layer (9a). A capacitor (20) having a highly dielectric film (15) is formed such that it is electrically connected to source/drain region (25) through plug layer (9a). The interlayer insulating film is formed of a two-layer structure including a silicon oxide film (1) and a silicon nitride film (3). Silicon nitride film (3) and plug layer (9a) have the top surfaces flush with each other.

摘要翻译： 本发明的目的是提供一种半导体器件，其具有具有良好的防漏电特性和良好的击穿电压特性的电容器，并且适用于高集成度。 源极/漏极区（25）形成在硅衬底（31）的表面。 在硅衬底（31）的表面上形成具有接触孔（1a）和（3a）的层间绝缘膜（1）和（3），源极/漏极区域的表面部分露出。 接触孔（1a）和（3a）填充有塞层（9a）。 具有高电介质膜（15）的电容器（20）形成为通过插塞层（9a）与源极/漏极区域（25）电连接。 层间绝缘膜由包括氧化硅膜（1）和氮化硅膜（3）的两层结构形成。 氮化硅膜（3）和插塞层（9a）的上表面彼此齐平。

公开(公告)号：US5693553A

公开(公告)日：1997-12-02

申请号：US689761

申请日：1996-08-13

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/11502 ,  Y10S257/90

摘要： An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.

摘要翻译： 本发明的目的是提供具有良好的防漏电特性和良好的击穿电压特性的电容器。 具有源极/漏极区域的传输栅极晶体管形成在硅衬底的表面上。 提供了一个下电极层，该下电极层通过填充形成在层间绝缘膜上的接触孔的插塞层连接到源/漏区。 在下电极层上形成电容绝缘层，该电容器绝缘层包括铁电体层，并暴露至少下电极层的侧壁表面。 下电极层的露出的侧壁表面被形成在层间绝缘膜的顶表面上并具有侧壁间隔物构造的侧壁绝缘层覆盖。 下电极层覆盖有上电极层，其间具有侧壁绝缘层和电容器绝缘层。

公开(公告)号：US5567964A

公开(公告)日：1996-10-22

申请号：US526392

申请日：1995-09-11

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/088 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/11502 ,  Y10S257/90

摘要： An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.

摘要翻译： 本发明的目的是提供具有良好的防漏电特性和良好的击穿电压特性的电容器。 具有源极/漏极区域的传输栅极晶体管形成在硅衬底的表面上。 提供了一个下电极层，该下电极层通过填充形成在层间绝缘膜上的接触孔的插塞层连接到源/漏区。 在下电极层上形成电容绝缘层，该电容器绝缘层包括铁电体层，并暴露至少下电极层的侧壁表面。 下电极层的露出的侧壁表面被形成在层间绝缘膜的顶表面上并具有侧壁间隔物构造的侧壁绝缘层覆盖。 下电极层覆盖有上电极层，其间具有侧壁绝缘层和电容器绝缘层。

公开(公告)号：US5382817A

公开(公告)日：1995-01-17

申请号：US20082

申请日：1993-02-19

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L21/02 ,  H01L27/115 ,  H01L29/92

CPC分类号： H01L27/11502 ,  H01L28/55 ,  H01L28/75 ,  Y10S257/915

摘要： A semiconductor device capable of improving pressure-resistant and leakage-resistant characteristics of a stacked type capacitor formed on a planarized insulating layer. The semiconductor device includes a plug electrode layer 313 of at least one material selected from the group consisting of TiN, Ti, W, and WN, buried in a contact hole 311a of an interlayer insulating films 311 and extending on and along the upper surface of interlayer insulating film 311. As a result, creation of a stepped portion on platinum layer 314 constituting a capacitor lower electrode to be formed on the plug electrode 313 is prevented, and the thickness of a PZT film 315 to be formed on platinum layer 314 is not disadvantageously made thin at the stepped portion. Therefore, the space between a capacitor upper electrode 316 and platinum layer 314 constituting the capacitor lower electrode can not be made narrow, and an electric field between platinum layer 314 and capacitor upper electrode 316 is made uniform, enhancing pressure-resistant and leakage-resistant characteristics. Also, a silicification reaction of platinum layer 314 is prevented due to plug electrode layer 313. In addition, when plug electrode layer 313 is formed of Ti or TiN, adhesion of plug electrode layer 313 and interlayer insulating film 311 is improved, and thus separation of platinum layer 314 is prevented.

摘要翻译： 一种能够提高形成在平坦化绝缘层上的叠层型电容器的耐压和耐漏电特性的半导体器件。 半导体器件包括从由TiN，Ti，W和WN组成的组中选择的至少一种材料的插塞电极层313，该TiN，Ti，W和WN埋在层间绝缘膜311的接触孔311a中并在其上表面上延伸 结果，防止了在形成在插头电极313上的构成电容器下电极的铂层314上形成台阶部分，并且形成在铂层314上的PZT膜315的厚度为 不利于在阶梯部分变薄。 因此，构成电容器下电极的电容器上电极316和铂层314之间的空间不能变窄，铂层314和电容器上电极316之间的电场均匀，增强耐压和耐漏电 特点 此外，由于塞电极层313，可防止铂层314的硅化反应。此外，当塞电极层313由Ti或TiN形成时，插塞电极层313和层间绝缘膜311的粘附性提高，因此分离 的铂层314。

公开(公告)号：US07700448B2

公开(公告)日：2010-04-20

申请号：US12014136

申请日：2008-01-15

申请人： Takuya Futase ,  Keiichiro Kashihara ,  Shigenari Okada

发明人： Takuya Futase ,  Keiichiro Kashihara ,  Shigenari Okada

IPC分类号： H01L21/00

CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7843

摘要： The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate. A barrier film is a film which makes a semiconductor substrate generate tensile stress, and the metal silicide layer which consists of mono-silicide MSi of metallic element M which forms a metallic film is formed in the first heat treatment.

摘要翻译： 提高了在自对准硅化物工艺中形成金属硅化物层的半导体器件的性能。 通过STI法在半导体衬底中形成元件隔离区域，形成栅极绝缘膜，形成栅电极，形成n +型半导体区域和形成用于源极/漏极的p +型半导体区域，金属膜形成在 半导体衬底和阻挡膜形成在金属膜上。 在形成通过进行第一热处理使金属膜和栅电极n +型半导体区域和p +型半导体区域形成反应的金属硅化物层之后，除去阻挡膜和未反应的金属膜， 留下金属硅化物层。 元件隔离区使压缩应力作用在半导体衬底上。 阻挡膜是使半导体基板产生拉伸应力的膜，在第一热处理中形成由形成金属膜的金属元素M的单硅化物MSi构成的金属硅化物层。

公开(公告)号：US08343827B2

公开(公告)日：2013-01-01

申请号：US13182750

申请日：2011-07-14

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Yoji Kawasaki

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Yoji Kawasaki

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.

摘要翻译： 在CMIS器件中，为了改善通过使用应变硅技术形成的n沟道电场晶体管的工作特性，而不降低p沟道场效应晶体管的工作特性。 在形成pISIS的nMIS和源极/漏极（p型延伸区域和p型扩散区域）的源极/漏极（n型延伸区域和n型扩散区域）之后， 源极/漏极具有所需的浓度分布和电阻，在n型扩散区域中形成具有所需量的应变的Si：C层，因此Si：C层中的最佳寄生电阻和最佳应变量 在nMIS的源/漏中获得。 此外，通过在等于或短于1毫秒的短时间内形成Si：C层进行热处理，已经形成的p型延伸区域的各个p型杂质的浓度分布的变化和 p型扩散区被抑制。