公开(公告)号：US5519237A

公开(公告)日：1996-05-21

申请号：US264117

申请日：1994-06-22

申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L29/68

CPC分类号： H01L27/10808

摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

公开(公告)号：US5753527A

公开(公告)日：1998-05-19

申请号：US613555

申请日：1996-03-11

申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10808

摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

公开(公告)号：US5693553A

公开(公告)日：1997-12-02

申请号：US689761

申请日：1996-08-13

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/11502 ,  Y10S257/90

摘要： An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.

摘要翻译： 本发明的目的是提供具有良好的防漏电特性和良好的击穿电压特性的电容器。 具有源极/漏极区域的传输栅极晶体管形成在硅衬底的表面上。 提供了一个下电极层，该下电极层通过填充形成在层间绝缘膜上的接触孔的插塞层连接到源/漏区。 在下电极层上形成电容绝缘层，该电容器绝缘层包括铁电体层，并暴露至少下电极层的侧壁表面。 下电极层的露出的侧壁表面被形成在层间绝缘膜的顶表面上并具有侧壁间隔物构造的侧壁绝缘层覆盖。 下电极层覆盖有上电极层，其间具有侧壁绝缘层和电容器绝缘层。

公开(公告)号：US5572052A

公开(公告)日：1996-11-05

申请号：US374890

申请日：1995-01-19

申请人： Keiichiro Kashihara ,  Tomonori Okudaira ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Tomonori Okudaira ,  Hiromi Itoh

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L29/92 ,  H01L29/94 ,  G11C11/22 ,  H01G4/06 ,  H01G4/20

CPC分类号： H01L27/11502 ,  H01L29/78391 ,  H01L29/92 ,  H01L29/94

摘要： In an electronic device using lead zirconate titanate (PZT) or lanthanum lead zirconate titanate (PLZT) as the main insulating material, a PZT film or a PLZT film is formed on a sub-insulating layer consisting essentially of lead titanate, lanthanum lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate, or lanthanum lead zirconate. In an MIS structure, a semiconductor, the sub-insulating layer, the PZT film and metal are deposited in order. In a capacitor, the sub-insulating layer and the PZT film are sandwiched between a pair of electrodes. The sub-insulating layer improves crystallinity of PZT or PLZT, and the dielectric constant. An oxide of Pb, La, Zr or Ti can be added as the sub-insulating layer in order to further suppress current leakage.

摘要翻译： 在使用锆钛酸铅（PZT）或锆钛酸镧铅（PLZT）作为主要绝缘材料的电子器件中，在主要由钛酸铅，钛酸镧铅，钛酸铅等构成的基础绝缘层上形成PZT膜或PLZT膜， 钛酸钡，钛酸锶，钛酸锶钡，锆酸铅或锆酸镧铅。 在MIS结构中，依次沉积半导体，次绝缘层，PZT膜和金属。 在电容器中，副绝缘层和PZT膜夹在一对电极之间。 亚绝缘层提高了PZT或PLZT的结晶度和介电常数。 可以添加Pb，La，Zr或Ti的氧化物作为副绝缘层，以进一步抑制电流泄漏。

公开(公告)号：US5567964A

公开(公告)日：1996-10-22

申请号：US526392

申请日：1995-09-11

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/088 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/11502 ,  Y10S257/90

摘要： An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.

摘要翻译： 本发明的目的是提供具有良好的防漏电特性和良好的击穿电压特性的电容器。 具有源极/漏极区域的传输栅极晶体管形成在硅衬底的表面上。 提供了一个下电极层，该下电极层通过填充形成在层间绝缘膜上的接触孔的插塞层连接到源/漏区。 在下电极层上形成电容绝缘层，该电容器绝缘层包括铁电体层，并暴露至少下电极层的侧壁表面。 下电极层的露出的侧壁表面被形成在层间绝缘膜的顶表面上并具有侧壁间隔物构造的侧壁绝缘层覆盖。 下电极层覆盖有上电极层，其间具有侧壁绝缘层和电容器绝缘层。

公开(公告)号：US5382817A

公开(公告)日：1995-01-17

申请号：US20082

申请日：1993-02-19

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L21/02 ,  H01L27/115 ,  H01L29/92

CPC分类号： H01L27/11502 ,  H01L28/55 ,  H01L28/75 ,  Y10S257/915

摘要： A semiconductor device capable of improving pressure-resistant and leakage-resistant characteristics of a stacked type capacitor formed on a planarized insulating layer. The semiconductor device includes a plug electrode layer 313 of at least one material selected from the group consisting of TiN, Ti, W, and WN, buried in a contact hole 311a of an interlayer insulating films 311 and extending on and along the upper surface of interlayer insulating film 311. As a result, creation of a stepped portion on platinum layer 314 constituting a capacitor lower electrode to be formed on the plug electrode 313 is prevented, and the thickness of a PZT film 315 to be formed on platinum layer 314 is not disadvantageously made thin at the stepped portion. Therefore, the space between a capacitor upper electrode 316 and platinum layer 314 constituting the capacitor lower electrode can not be made narrow, and an electric field between platinum layer 314 and capacitor upper electrode 316 is made uniform, enhancing pressure-resistant and leakage-resistant characteristics. Also, a silicification reaction of platinum layer 314 is prevented due to plug electrode layer 313. In addition, when plug electrode layer 313 is formed of Ti or TiN, adhesion of plug electrode layer 313 and interlayer insulating film 311 is improved, and thus separation of platinum layer 314 is prevented.

摘要翻译： 一种能够提高形成在平坦化绝缘层上的叠层型电容器的耐压和耐漏电特性的半导体器件。 半导体器件包括从由TiN，Ti，W和WN组成的组中选择的至少一种材料的插塞电极层313，该TiN，Ti，W和WN埋在层间绝缘膜311的接触孔311a中并在其上表面上延伸 结果，防止了在形成在插头电极313上的构成电容器下电极的铂层314上形成台阶部分，并且形成在铂层314上的PZT膜315的厚度为 不利于在阶梯部分变薄。 因此，构成电容器下电极的电容器上电极316和铂层314之间的空间不能变窄，铂层314和电容器上电极316之间的电场均匀，增强耐压和耐漏电 特点 此外，由于塞电极层313，可防止铂层314的硅化反应。此外，当塞电极层313由Ti或TiN形成时，插塞电极层313和层间绝缘膜311的粘附性提高，因此分离 的铂层314。

公开(公告)号：US06746876B2

公开(公告)日：2004-06-08

申请号：US10310765

申请日：2002-12-06

申请人： Hiromi Itoh ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara ,  Akie Yutani ,  Tomonori Okudaira

发明人： Hiromi Itoh ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara ,  Akie Yutani ,  Tomonori Okudaira

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  H01L28/91

摘要： A method for manufacturing a capacitor is provided which can form a lower electrode having a high aspect ratio without suffering deterioration of the capacitor electric characteristics even when a platinum-group metal is adopted as the material of the lower electrode and a metal oxide having a high dielectric constant is adopted as the material of the dielectric film. Holes (8) that reach contact plugs (2) are formed in an insulating film (7). Then a dielectric film (9) is formed on the surfaces of the holes (8). Next the dielectric film (9) on the bottoms of the holes (8) are etched away to form holes (18) reaching the contact plugs (2). Lower electrodes (11) are then formed to fill the holes (8) and (18).

摘要翻译： 提供了一种用于制造电容器的方法，即使当采用铂族金属作为下电极的材料时，也可形成具有高纵横比的下电极，而不会降低电容器的电特性，并且具有高的金属氧化物 采用介电常数作为电介质膜的材料。 到达接触塞（2）的孔（8）形成在绝缘膜（7）中。 然后在孔（8）的表面上形成介电膜（9）。 接下来，蚀刻掉孔（8）的底部上的电介质膜（9），以形成到达接触塞（2）的孔（18）。 然后形成下电极（11）以填充孔（8）和（18）。

公开(公告)号：US5972748A

公开(公告)日：1999-10-26

申请号：US969963

申请日：1997-11-25

申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10808

摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

公开(公告)号：US07700448B2

公开(公告)日：2010-04-20

申请号：US12014136

申请日：2008-01-15

申请人： Takuya Futase ,  Keiichiro Kashihara ,  Shigenari Okada

发明人： Takuya Futase ,  Keiichiro Kashihara ,  Shigenari Okada

IPC分类号： H01L21/00

CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7843

摘要： The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate. A barrier film is a film which makes a semiconductor substrate generate tensile stress, and the metal silicide layer which consists of mono-silicide MSi of metallic element M which forms a metallic film is formed in the first heat treatment.

摘要翻译： 提高了在自对准硅化物工艺中形成金属硅化物层的半导体器件的性能。 通过STI法在半导体衬底中形成元件隔离区域，形成栅极绝缘膜，形成栅电极，形成n +型半导体区域和形成用于源极/漏极的p +型半导体区域，金属膜形成在 半导体衬底和阻挡膜形成在金属膜上。 在形成通过进行第一热处理使金属膜和栅电极n +型半导体区域和p +型半导体区域形成反应的金属硅化物层之后，除去阻挡膜和未反应的金属膜， 留下金属硅化物层。 元件隔离区使压缩应力作用在半导体衬底上。 阻挡膜是使半导体基板产生拉伸应力的膜，在第一热处理中形成由形成金属膜的金属元素M的单硅化物MSi构成的金属硅化物层。

公开(公告)号：US5668041A

公开(公告)日：1997-09-16

申请号：US632194

申请日：1996-04-15

申请人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/04 ,  H01L27/105 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/3205 ,  H01L28/40 ,  H01L28/55 ,  Y10S257/915 ,  Y10S438/978

摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。