公开(公告)号：US5879977A

公开(公告)日：1999-03-09

申请号：US636819

申请日：1996-04-23

申请人： Hongyong Zhang ,  Hideki Uochi ,  Toru Takayama ,  Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Hongyong Zhang ,  Hideki Uochi ,  Toru Takayama ,  Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： H01L21/20 ,  H01L21/00 ,  H01L21/324 ,  H01L21/336 ,  H01L27/12 ,  H01L29/02 ,  H01L29/78 ,  H01L29/786 ,  H01L21/10

CPC分类号： H01L21/2022 ,  H01L27/1281 ,  H01L29/66757

摘要： A process for fabricating a semiconductor by crystallizing a silicon film in a substantially amorphous state by annealing it at a temperature not higher than the crystallization temperature of amorphous silicon, and it comprises forming selectively, on the surface or under an amorphous silicon film, a coating, particles, clusters, and the like containing nickel, iron, cobalt, platinum or palladium either as a pure metal or a compound thereof such as a silicide, a salt, and the like, shaped into island-like portions, linear portions, stripes, or dots; and then annealing the resulting structure at a temperature lower than the crystallization temperature of an amorphous silicon by 20.degree. to 150.degree. C.

摘要翻译： 一种通过在不高于非晶硅的结晶温度的温度下进行退火将基本无定形态的硅膜结晶化的半导体制造方法，其包括在表面上或非晶硅膜下选择性地形成涂层 ，含有镍，铁，钴，铂或钯的颗粒，簇等作为纯金属或其化合物，例如硅化物，盐等，成形为岛状部分，线状部分，条纹 ，或点; 然后在低于非晶硅的结晶温度的温度下将所得结构退火20〜150℃。

公开(公告)号：US5639698A

公开(公告)日：1997-06-17

申请号：US196856

申请日：1994-02-15

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Toru Takayama ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Toru Takayama ,  Hideki Uochi

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/2022 ,  H01L21/2026 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78618

摘要： Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

摘要翻译： 通过在低于非晶硅的正常结晶温度或低于基板的玻璃化转变点的温度下退火基本非晶硅膜以使硅膜结晶的方法来制造诸如薄膜晶体管的半导体器件。 镍，铁，钴或铂的岛，条纹，线或点，镍，铁，钴或铂的硅化物，乙酸盐或硝酸盐，含有各种盐，包含至少一种镍， 铁，钴和铂用作结晶的起始原料。 这些材料形成在非晶硅膜上或下方。

公开(公告)号：US08198683B2

公开(公告)日：2012-06-12

申请号：US12958739

申请日：2010-12-02

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US07847355B2

公开(公告)日：2010-12-07

申请号：US12534382

申请日：2009-08-03

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US07525158B2

公开(公告)日：2009-04-28

申请号：US10893889

申请日：2004-07-20

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US06906383B1

公开(公告)日：2005-06-14

申请号：US09526486

申请日：2000-03-15

申请人： Hongyong Zhang ,  Yasuhiko Takemura ,  Toshimitsu Konuma ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi

发明人： Hongyong Zhang ,  Yasuhiko Takemura ,  Toshimitsu Konuma ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L31/20 ,  H01L27/01

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

公开(公告)号：US06867431B2

公开(公告)日：2005-03-15

申请号：US08307167

申请日：1994-09-16

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/321 ,  H01L21/336 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0368 ,  H01L31/0392

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

公开(公告)号：US6013928A

公开(公告)日：2000-01-11

申请号：US479393

申请日：1995-06-07

申请人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

发明人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

IPC分类号： G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H04N3/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L29/04

CPC分类号： H04N3/127 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78618 ,  G02F1/1368 ,  G02F2001/136245 ,  G09G2300/0823

摘要： An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

摘要翻译： 一种适用于有源矩阵液晶显示器的绝缘栅场效应晶体管。 沟道长度或源极区域和漏极区域之间的距离大于沿着沟道的纵向方向取得的栅电极的长度。 偏移区域形成在源极和漏极区域的侧面上的沟道区域中。 没有或非常弱的电场被施加到来自栅电极的这些偏移区域。

公开(公告)号：US07635895B2

公开(公告)日：2009-12-22

申请号：US11647179

申请日：2006-12-29

申请人： Hongyong Zhang ,  Yasuhiko Takemura ,  Toshimitsu Konuma ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi

发明人： Hongyong Zhang ,  Yasuhiko Takemura ,  Toshimitsu Konuma ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi

IPC分类号： H01L27/12

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

摘要翻译： 提供了一种方法，通过该方法可以容易地形成轻掺杂漏极（LDD）区域，并且在具有覆盖有氧化物覆盖层的栅电极的薄膜晶体管中的源/漏区域中以良好的产率形成。 通过以栅极电极作为掩模，以自对准的方式将杂质引入岛状硅膜中形成轻掺杂漏极（LDD）区域。 首先，通过使用旋转 - 倾斜离子注入在岛状硅膜中形成低浓度杂质区，以相对于衬底从倾斜方向进行离子掺杂。 此时也在栅电极下方形成低浓度杂质区。 之后，将高浓度的杂质通常引入衬底，从而形成高浓度杂质区域。 在上述过程中，低浓度杂质区域保留在栅电极下方并构成轻掺杂漏区。

公开(公告)号：US07381599B2

公开(公告)日：2008-06-03

申请号：US11064821

申请日：2005-02-25

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。