公开(公告)号：US07800152B2

公开(公告)日：2010-09-21

申请号：US11835182

申请日：2007-08-07

申请人： Huilong Zhu ,  Bruce B. Doris

发明人： Huilong Zhu ,  Bruce B. Doris

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided.

摘要翻译： 提供了一种使用薄SiGe层在半导体衬底上制造鳍结构以在硅衬底和硅片部分之间产生空隙的方法。 还提供了通过这种方法制造的翅片结构。

公开(公告)号：US07767503B2

公开(公告)日：2010-08-03

申请号：US12132853

申请日：2008-06-04

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20080242069A1

公开(公告)日：2008-10-02

申请号：US12132853

申请日：2008-06-04

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US07354806B2

公开(公告)日：2008-04-08

申请号：US10711416

申请日：2004-09-17

申请人： Bruce B. Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

IPC分类号： H01L21/00

CPC分类号： H01L29/045 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7842

摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.

摘要翻译： 公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。 该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。 半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个 其他。

公开(公告)号：US07314802B2

公开(公告)日：2008-01-01

申请号：US11669598

申请日：2007-01-31

申请人： Huilong Zhu ,  Bruce B. Doris

发明人： Huilong Zhu ,  Bruce B. Doris

IPC分类号： H01L21/336 ,  H01L21/00 ,  H01L21/84 ,  H01L21/338

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7842 ,  H01L29/7854 ,  H01L29/78645 ,  H01L2924/0002 ,  H01L2924/00

摘要： A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively etched to form a gate gap that makes the gate thin enough to be fully silicidated. After silicidation, the gate-gap is filled with a stress nitride film to create stress in the channel and enhance the performance of the FINFET.

摘要翻译： FINFET栅极的一部分由应力材料代替，以对FINFET的沟道施加应力，以增强电子和空穴的迁移率并提高性能。 FINFET具有SiGe / Si堆叠栅极，并且在硅化之前，选择性地蚀刻栅极的SiGe部分以形成栅极间隙，使得栅极足够薄以完全硅化。 在硅化之后，栅间隙填充有应力氮化物膜，以在沟道中产生应力并增强FINFET的性能。

公开(公告)号：US07183613B1

公开(公告)日：2007-02-27

申请号：US11164224

申请日：2005-11-15

申请人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

发明人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

IPC分类号： H01L27/01

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

摘要翻译： 用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极堆叠每个都由在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。

公开(公告)号：US07094634B2

公开(公告)日：2006-08-22

申请号：US10710277

申请日：2004-06-30

申请人： Huilong Zhu ,  Bruce B. Doris ,  Meikei Ieong ,  Phillip J. Oldiges ,  Min Yang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Meikei Ieong ,  Phillip J. Oldiges ,  Min Yang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/76254 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785 ,  Y10T428/249921 ,  Y10T428/249922

摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

公开(公告)号：US06939751B2

公开(公告)日：2005-09-06

申请号：US10605726

申请日：2003-10-22

申请人： Huilong Zhu ,  Bruce B. Doris ,  Werner A. Rausch ,  Ying Zhang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Werner A. Rausch ,  Ying Zhang

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66621 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78687

摘要： An RSD FET device with a recessed channel is formed with a raised silicon sources and drains and a gate electrode structure formed on an SOI structure (a Si layer formed on a substrate) by the steps as follows. Form a SiGe layer over the Si layer and a RSD layer over the SiGe. Etch through the RSD layer and the SiGe to form a gate electrode space reaching down the Si layer. Form a pair of RSD regions separated by the gate electrode space. Line the walls of the gate electrode space with an internal etch stop layer and an inner sidewall spacers. Form a gate electrode inside the inner sidewall spacers on the Si layer. Form external sidewall spacers adjacent to the gate electrode between the RSD regions next to the inner sidewall spacers, and dope the RSD regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions thereabove and below the level of the SiGe layer.

摘要翻译： 具有凹陷沟道的RSD FET器件通过以下步骤形成有凸起的硅源和漏极以及形成在SOI结构（形成在衬底上的Si层）上的栅电极结构。 在Si层上形成SiGe层，在SiGe上形成RSD层。 通过RSD层和SiGe蚀刻以形成向下延伸到Si层的栅电极空间。 形成一对被栅电极间隔开的RSD区域。 用内部蚀刻停止层和内侧壁间隔物来排列栅电极空间的壁。 在Si层上的内侧墙壁内部形成栅电极。 在靠近内侧壁间隔物的RSD区域之间形成与栅电极相邻的外侧壁间隔物，并且掺杂RSD区域，由此在SOI硅层之间形成凹陷沟道，在SOI硅层之间的上升源极/漏极区域之间并且低于 SiGe层。

公开(公告)号：US07732874B2

公开(公告)日：2010-06-08

申请号：US11847573

申请日：2007-08-30

申请人： Huilong Zhu ,  Bruce B. Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L29/423

CPC分类号： H01L27/1211 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/785

摘要： A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.

摘要翻译： 半导体结构包括第一finFET和第二finFET。 第一finFET和第二finFET可以包括n-finFET和p-finFET，以提供CMOS finFET结构。 在半导体结构内，以下至少一个：（1）第一鳍状FET内的第一栅极电介质和第二鳍状FET内的第二栅极电介质包括不同的栅极电介质材料; 和/或（2）第一鳍状FET内的第一栅电极和第二鳍状FET内的第二栅电极包括不同的栅电极材料。

公开(公告)号：US07504693B2

公开(公告)日：2009-03-17

申请号：US10709239

申请日：2004-04-23

申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L23/62 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7845 ,  H01L21/28035 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/7842

摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

摘要翻译： 公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。