公开(公告)号：US11429469B2

公开(公告)日：2022-08-30

申请号：US17195579

申请日：2021-03-08

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Ravi H. Motwani ,  Chang Wan Ha

IPC: G06F11/07 ,  G11C16/34 ,  G11C7/12 ,  G11C16/14 ,  G11C29/44

Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

公开(公告)号：US10923622B2

公开(公告)日：2021-02-16

申请号：US16563558

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  Ali Khakifirooz

IPC: H01L33/02 ,  H01L33/38 ,  H01L33/06 ,  H01L33/04 ,  H01L33/24 ,  H01L27/15 ,  H01L33/18 ,  H01L33/32 ,  H01L25/075 ,  H01L33/56

Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, a pixel element for a micro-light emitting diode (LED) display panel includes a first color nanowire LED, a second color nanowire LED, the second color different than the first color, and a pair of third color nanowire LEDs, the third color different than the first and second colors. A continuous insulating material layer ius laterally surrounding the first color nanowire LED, the second color nanowire LED, and the pair of third color nanowire LEDs.

公开(公告)号：US20190180829A1

公开(公告)日：2019-06-13

申请号：US16276695

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Lei Chen ,  Xin Guo ,  Ali Khakifirooz ,  Aliasgar Madraswala ,  Yogesh B. Wakchaure

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/22 ,  G06F11/07

Abstract: An embodiment of a semiconductor apparatus may include technology to determine an error rate associated with a read request for a persistent storage media, compare the determined error rate against a pre-fail threshold, and adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold. Other embodiments are disclosed and claimed.

公开(公告)号：US20190041656A1

公开(公告)日：2019-02-07

申请号：US16022158

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Ali Khakifirooz ,  Prashant Majhi ,  Kunjal Parikh

IPC: G02B27/42 ,  H01L21/02 ,  H01L21/762 ,  G06T19/00 ,  H01L27/01 ,  G02B27/01

Abstract: Diffractive optical elements for wide field-of-view virtual reality devices and methods of manufacturing the same are disclosed. An example apparatus includes a substrate and a thin film stack including alternating layers of a first material and a second material. The thin film stack defines an annular protrusion. The annular protrusion has a stair-like profile. Top surfaces of separate ones of steps in the stair-like profile correspond to top surfaces of separate ones of the layers of the second material.

公开(公告)号：US09806127B1

公开(公告)日：2017-10-31

申请号：US15381943

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Ali Khakifirooz

IPC: H01L33/00 ,  H01L27/15 ,  H01L33/46 ,  H01L33/32 ,  H01L33/06 ,  H01L33/42

CPC classification number: H01L27/156 ,  H01L33/007 ,  H01L33/08 ,  H01L33/24 ,  H01L33/32 ,  H01L33/46

Abstract: Embodiments related to light emitting diodes having an electron transport layer core with first and second opposite sidewalls extending from a proximal end of the electron transport layer core adjacent to the substrate to a distal end of the electron transport layer core extending away from the substrate, an emission layer disposed on both the first and second sidewalls, and a hole transport layer disposed on the emission layer, displays having such light emitting diodes, systems incorporating such light emitting diodes, and methods for fabricating them are discussed.

公开(公告)号：US12224019B2

公开(公告)日：2025-02-11

申请号：US17213150

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G11C16/00 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

公开(公告)号：US20220310160A1

公开(公告)日：2022-09-29

申请号：US17212792

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu Rajwade ,  Tarek Ahmed Ameen Beshari

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/24 ,  G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.

公开(公告)号：US10276252B2

公开(公告)日：2019-04-30

申请号：US15838202

申请日：2017-12-11

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Ali Khakifirooz ,  Pranav Kalavade ,  Sagar Upadhyay

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/22 ,  G11C16/10 ,  G11C11/56

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.