公开(公告)号：US20250006839A1

公开(公告)日：2025-01-02

申请号：US18343203

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  Rachel A. Steinhardt ,  Pratyush P. Buragohain ,  John J. Plombon ,  Hai Li ,  Gauri Auluck ,  I-Cheng Tung ,  Tristan A. Tronic ,  Dominique A. Adams ,  Punyashloka Debashis ,  Raseong Kim ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Marko Radosavljevic ,  Uygar E. Avci ,  Ian Alexander Young ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20230284538A1

公开(公告)日：2023-09-07

申请号：US17685053

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Chia-Ching Lin ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/06 ,  H01L27/22 ,  H01L43/14 ,  H01F10/32 ,  G11C11/18 ,  G11C11/16 ,  H03K19/18

CPC classification number: H01L43/06 ,  H01L27/228 ,  H01L43/14 ,  H01F10/3286 ,  H01F10/3268 ,  G11C11/18 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/18 ,  H01L43/10

Abstract: A spin orbit logic device includes: a first electrically conductive layer; a layer including a magnetoelectric material (ME layer) on the first electrically conductive layer; a layer including a ferromagnetic material with in-plane magnetic anisotropy (FM layer) on the ME layer; a second electrically conductive layer on the FM layer; a layer including a dielectric material on the second electrically conductive layer (coupling layer); a layer including a spin orbit coupling material (SOC layer) on the coupling layer; and a layer including a ferromagnetic material with perpendicular magnetic anisotropy (PMA layer) on the SOC layer.

公开(公告)号：US20230077177A1

公开(公告)日：2023-03-09

申请号：US17469320

申请日：2021-09-08

Applicant: Intel Corporation

Inventor： Hai Li ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Tanay A. Gosavi ,  Ian Alexander Young

IPC: H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L25/10

Abstract: A spin orbit logic (SOL) device includes a first electrically conductive layer; a layer comprising a ferroelectric material (FE layer) on the first electrically conductive layer; a second electrically conductive layer on the FE layer; and a spin orbit coupling (SOC) stack including a first layer (SOC1 layer) including a first SOC material, and a second layer (SOC2 layer) including a second SOC material, the SOC1 layer adjacent the FE layer.

公开(公告)号：US20230070486A1

公开(公告)日：2023-03-09

申请号：US17467124

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Hai Li

IPC: G11C11/16 ,  G06F7/58 ,  G06F17/16

Abstract: Technologies for non-uniform random number generation are disclosed. In one embodiment, the distribution of resistance of a magnetic tunnel junction (MTJ) can be controlled by applying a mechanical strain with a piezoelectric layer and by applying a spin torque by a spin-orbit torque layer. The distribution of resistance can be approximately a Gaussian distribution. In another embodiment, an array of N probabilistic bits (p-bits) has a bias and feedback matrix that result in the array of p-bits outputting an N-bit random number with a non-uniform distribution, such as a Gaussian distribution.

公开(公告)号：US20230068950A1

公开(公告)日：2023-03-02

申请号：US17405953

申请日：2021-08-18

Applicant: Intel Corporation

Inventor： Dmitri Evgenievich Nikonov ,  Hai Li ,  Ian Alexander Young

IPC: H01L29/78 ,  H01L29/10 ,  H03K19/00

Abstract: A leakage insensitive transistor includes a substrate, a source region, a drain region, a channel region between the source region and drain region, a gate dielectric on the channel region, first and second electrodes on the gate dielectric, and third and fourth electrodes on the substrate. The leakage insensitive transistor may be operated by applying a first logic signal to the first electrode, floating the second electrode of the FET, applying a second logic signal opposite the first logic signal to the third electrode, and floating the fourth electrode. A logic circuit may include multiple leakage insensitive transistors.

公开(公告)号：US20220115438A1

公开(公告)日：2022-04-14

申请号：US17070808

申请日：2020-10-14

Applicant: Intel Corporation

Inventor： Hai Li ,  Dmitri Nikonov ,  Chia-Ching Lin ,  Tanay Gosavi ,  Ian Young

IPC: H01L27/22 ,  H01F10/32

Abstract: A differential magnetoelectric spin-orbit (MESO) logic device is provided where two ports are used to connect the spin orbital module of the MESO device and a ferroelectric capacitor. In some examples, an insulating layer is added to decouple current paths.