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    Techniques for accelerating memory access operations
    21.
    发明授权
    Techniques for accelerating memory access operations 有权

    公开(公告)号：US11422954B2

    公开(公告)日：2022-08-23

    申请号：US16147241

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Robert Pelt ,  Arifur Rahman ,  Hong Wang

    IPC: G06F13/16 ,  G06F12/0862 ,  G06F13/28

    Abstract: A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.

    AUTOMATIC PREDICATION OF HARD-TO-PREDICT CONVERGENT BRANCHES
    25.
    发明申请
    AUTOMATIC PREDICATION OF HARD-TO-PREDICT CONVERGENT BRANCHES 审中-公开

    公开(公告)号：US20200004542A1

    公开(公告)日：2020-01-02

    申请号：US16021838

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Zeev Sperber ,  Sumeet Bandishte ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Kamil Garifullin ,  Sreenivas Subramoney ,  Adi Yoaz ,  Hong Wang

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

    Instruction and logic for nearest neighbor unit
    26.
    发明授权
    Instruction and logic for nearest neighbor unit 有权

    公开(公告)号：US10387797B2

    公开(公告)日：2019-08-20

    申请号：US14865124

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Tsung-Han Lin ,  Gokce Keskin ,  Hsiang-Tsung Kung ,  She-Hwa Yen ,  Hong Wang

    IPC: G06F15/18 ,  G06N20/00 ,  G06F9/30

    Abstract: A processor includes a front end to decode an instruction, an allocator to pass the instruction to a nearest neighbor logic unit (NNLU) to execute the instruction, and a retirement unit to retire the instruction. The NNLU includes logic to determine input of the instruction for which nearest neighbors will be calculated, transform the input, retrieve candidate atoms for which the nearest neighbors will be calculated, compute distance between the candidate atoms and the input, and determine the nearest neighbors for the input based upon the computed distance.

    RUNTIME PROCESSOR OPTIMIZATION
    27.
    发明申请
    RUNTIME PROCESSOR OPTIMIZATION 审中-公开

    公开(公告)号：US20180246762A1

    公开(公告)日：2018-08-30

    申请号：US15444390

    申请日：2017-02-28

    Applicant: Intel Corporation

    Inventor： Stephen J. Tarsa ,  Gautham N. Chinya ,  Gokce Keskin ,  Hong Wang ,  Karthik Sankaranarayanan

    IPC: G06F9/50

    CPC classification number: G06F9/5083

    Abstract: In one embodiment, a processor comprises a processor optimization unit. The processor optimization unit is to collect runtime information associated with a computing device, wherein the runtime information comprises information indicating a performance of the computing device during program execution. The processor optimization unit is further to receive runtime optimization information for the computing device, wherein the runtime optimization information comprises information associated with one or more runtime optimizations for the computing device, and wherein the runtime optimization information is determined based on an analysis of the collected runtime information. The processor optimization unit is further to perform the one or more runtime optimizations for the computing device based on the runtime optimization information.

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