公开(公告)号：US20240332389A1

公开(公告)日：2024-10-03

申请号：US18736428

申请日：2024-06-06

Applicant: Intel Corporation

Inventor： Nicole THOMAS ,  Michael K. HARPER ,  Leonard P. GULER ,  Marko RADOSAVLJEVIC ,  Thoe MICHAELOS

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/0228 ,  H01L21/76897 ,  H01L21/823412 ,  H01L29/0669

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.

公开(公告)号：US20240222440A1

公开(公告)日：2024-07-04

申请号：US18089919

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Han Wui THEN ,  Ibrahim BAN ,  Heli Chetanbhai VORA ,  Marko RADOSAVLJEVIC

IPC: H01L29/267 ,  H01L21/02 ,  H01L21/18 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/0254 ,  H01L21/185 ,  H01L21/32051 ,  H01L29/0607 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for using layer transfer techniques to bond a silicon layer with a GaN layer, where the silicon layer includes a first portion of a device, for example a transistor, and the GaN layer includes a second portion of the device. Other embodiments may be described and/or claimed.

公开(公告)号：US20240021725A1

公开(公告)日：2024-01-18

申请号：US18088546

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Samuel James BADER ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Heli Chetanbhai VORA ,  Ahmad ZUBAIR

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L29/66462 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/4236

Abstract: Gallium nitride (GaN) transistors with lateral depletion for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen above a silicon substrate, a gate structure over the layer including gallium and nitrogen, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, and a source field plate laterally between the gate structure and the drain region, the source field plate laterally separated from the gate structure.

公开(公告)号：US20230066336A1

公开(公告)日：2023-03-02

申请号：US17458112

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Kimin JUN ,  Thomas HOFF ,  Han Wui THEN ,  Nicole K. THOMAS ,  Marko RADOSAVLJEVIC ,  Paul B. FISCHER

IPC: H01L27/06 ,  H01L29/26 ,  H01L23/48 ,  H01L49/02 ,  H01L29/778 ,  H01L29/04 ,  H01L21/8258 ,  H01L21/822

Abstract: Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

公开(公告)号：US20230054719A1

公开(公告)日：2023-02-23

申请号：US17408025

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Souvik GHOSH ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Ibrahim BAN ,  Kimin JUN ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/20

Abstract: Gallium nitride (GaN) layer transfer and regrowth for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate. An insulator layer is over the substrate. A device layer is directly on the insulator layer. The device layer has a thickness of less than approximately 500 nanometers.

公开(公告)号：US20220262796A1

公开(公告)日：2022-08-18

申请号：US17731110

申请日：2022-04-27

Applicant: Intel Corporation

Inventor： Nicole THOMAS ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

公开(公告)号：US20200235216A1

公开(公告)日：2020-07-23

申请号：US16630143

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/423 ,  H01L29/778 ,  H01L29/20 ,  H03F3/193

Abstract: Gallium nitride transistors having multiple threshold voltages are described. In an example, a transistor includes a gallium nitride layer over a substrate, a gate stack over the gallium nitride layer, a source region on a first side of the gate stack, and a drain region on a second side of the gate stack, the second side opposite the first side, wherein the gate stack has a gate length in a first direction extending from the source region to the drain region, the gate stack having a gate width in a second direction perpendicular to the first direction and parallel to the source region and the drain region. The transistor also includes a polarization layer beneath the gate stack and on the GaN layer, the polarization layer having a first portion having a first thickness under a first gate portion and a second thickness under a second gate portion.

公开(公告)号：US20190393319A1

公开(公告)日：2019-12-26

申请号：US16016391

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/51 ,  H01L21/285

Abstract: A transistor is disclosed. The transistor includes a first part of a gate above a substrate that has a first width and a second part of the gate above the first part of the gate that is centered with respect to the first part of the gate and that has a second width that is greater than the first width. The first part of the gate and the second part of the gate form a single monolithic T-gate structure.

公开(公告)号：US20190259806A1

公开(公告)日：2019-08-22

申请号：US16347724

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Paul FISCHER ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Edris MOHAMMED

IPC: H01L27/20 ,  H03H3/08 ,  H03H9/02 ,  H03H9/10 ,  H03H9/145 ,  H03H9/25

Abstract: A surface acoustic wave (SAW) resonator structure, an integrated circuit, and a method of fabricating a SAW structure are provided. The method includes epitaxially growing a crystalline aluminum nitride piezoelectric film layer on a substrate; and deposing a plurality of electrodes on the piezoelectric film layer. The SAW structure includes a substrate, a piezoelectric film on the substrate, and a plurality of electrodes on the piezoelectric film.

公开(公告)号：US20190244936A1

公开(公告)日：2019-08-08

申请号：US16386200

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Valluri RAO ,  Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Jack KAVALIEROS

IPC: H01L25/07 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8258 ,  H01L29/778 ,  H01L25/00 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.