公开(公告)号：US20240030116A1

公开(公告)日：2024-01-25

申请号：US18375133

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/29

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20230343716A1

公开(公告)日：2023-10-26

申请号：US18216102

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Amr ELSHAZLY ,  Arun CHANDRASEKHAR ,  Shawna M. LIFF ,  Johanna M. SWAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/00 ,  H01L2224/16225 ,  H01L2224/1703

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20220415839A1

公开(公告)日：2022-12-29

申请号：US17357722

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Feras EID ,  Johanna M. SWAN ,  Adel A. ELSHERBINI ,  Shawna M. LIFF

IPC: H01L23/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.

公开(公告)号：US20210193583A1

公开(公告)日：2021-06-24

申请号：US17192462

申请日：2021-03-04

Applicant: INTEL CORPORATION

Inventor： Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Shawna M. LIFF ,  Henning BRAUNISCH ,  Krishna BHARATH ,  Javier SOTO GONZALEZ ,  Javier A. FALCON

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L23/498

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US20200273839A1

公开(公告)日：2020-08-27

申请号：US16647863

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20200273784A1

公开(公告)日：2020-08-27

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20200064555A1

公开(公告)日：2020-02-27

申请号：US16072240

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sasha N. OSTER ,  Johanna M. SWAN ,  Feras EID ,  Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Baris BICEN ,  Valluri R. RAO

IPC: G02B6/35 ,  H04Q11/00 ,  H04B10/25

Abstract: Embodiments of the invention include an optical routing device that includes an organic substrate. According to an embodiment, an array of cavities are formed into the organic substrate and an array of piezoelectrically actuated mirrors may be anchored to the organic substrate with each piezoelectrically actuated mirror extending over a cavity. In order to properly rout incoming optical signals, the optical routing device may also include a routing die mounted on the organic substrate. The routing die may be electrically coupled to each of the piezoelectrically actuated mirrors and is able to generated a voltage across the first and second electrodes of each piezoelectrically actuated mirror. Additionally, a photodetector may be electrically coupled to the routing die. According to an embodiment, an array of fiber optic cables may be optically coupled with one of the piezoelectrically actuated mirrors and optically coupled with the photodetector.

公开(公告)号：US20190252597A1

公开(公告)日：2019-08-15

申请号：US16397356

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Feras EID ,  Shawna M. LIFF

IPC: H01L41/053 ,  H01L41/047 ,  H01L41/23

CPC classification number: H01L41/0533 ,  H01L41/047 ,  H01L41/094 ,  H01L41/23 ,  H01L41/332 ,  H03H9/10

Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.

公开(公告)号：US20190036004A1

公开(公告)日：2019-01-31

申请号：US16071992

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Feras EID ,  Sasha N. OSTER ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Valluri R. RAO ,  Baris BICEN

IPC: H01L41/113 ,  H01L41/047 ,  H01L41/253 ,  H01L41/29 ,  H01L41/316 ,  H01L41/332 ,  H01L41/317 ,  H01L27/20 ,  G01L1/16

Abstract: Embodiments of the invention include a piezoelectric sensor system. According to an embodiment of the invention, the piezoelectric sensor system may include a piezoelectric sensor, a signal conditioning circuit, and a light source each formed on an organic or flexible substrate. In embodiments of the invention, the piezoelectric sensor may be a discrete component or the piezo electric sensor may be integrated into the substrate. According to an embodiment, a piezoelectric sensor that is integrated into the substrate may comprise, a cavity formed into the organic substrate and a moveable beam formed over the cavity and anchored to the organic substrate. Additionally, the piezoelectric sensor may include a piezoelectric region formed over an end portion of the moveable beam and extending at least partially over the cavity. The piezoelectric sensor may also include a top electrode formed over a top surface of the piezoelectric region.

公开(公告)号：US20180337135A1

公开(公告)日：2018-11-22

申请号：US15776773

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L23/552 ,  H01L25/16 ,  H01L23/498 ,  H01L23/13 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.