公开(公告)号：US20210193583A1

公开(公告)日：2021-06-24

申请号：US17192462

申请日：2021-03-04

Applicant: INTEL CORPORATION

Inventor： Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Shawna M. LIFF ,  Henning BRAUNISCH ,  Krishna BHARATH ,  Javier SOTO GONZALEZ ,  Javier A. FALCON

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L23/498

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US20200273839A1

公开(公告)日：2020-08-27

申请号：US16647863

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20240038671A1

公开(公告)日：2024-02-01

申请号：US18377991

申请日：2023-10-09

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/5381 ,  H01L23/13 ,  H01L24/14 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L21/6835

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20190150291A1

公开(公告)日：2019-05-16

申请号：US16230977

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Brandon M. RAWLINGS ,  Henning BRAUNISCH

IPC: H05K3/00 ,  H05K3/46

Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

公开(公告)号：US20170287808A1

公开(公告)日：2017-10-05

申请号：US15625947

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Feras EID ,  Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Don W. NELSON

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/52 ,  H01L23/473

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/021 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10416 ,  H05K2201/10545 ,  H01L2924/00

Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.

公开(公告)号：US20160211190A1

公开(公告)日：2016-07-21

申请号：US14914998

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Henning BRAUNISCH ,  Feras EID ,  Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Don W. NELSON

IPC: H01L23/367 ,  H01L21/52 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/021 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10416 ,  H05K2201/10545 ,  H01L2924/00

Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.

Abstract translation: 一种包括模具的设备，所述模具的第一侧包括第一类型的系统级接触点和包括第二类型的接触点的第二侧; 以及耦合到管芯和管芯的第二侧的封装衬底。 一种包括管芯的设备，所述管芯的第一侧包括多个系统级逻辑接触点和包括第二多个系统级电力接触点的第二侧。 一种方法，包括将管芯的第一侧上的第一类型的系统级接触点中的一个与管芯的第二侧上的第二类型的系统级接触点耦合到封装衬底。

公开(公告)号：US20160183370A1

公开(公告)日：2016-06-23

申请号：US14576107

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Brandon M. Rawlings ,  Henning BRAUNISCH

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/06 ,  H05K3/40 ,  H05K3/02 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K3/0082 ,  H05K1/116 ,  H05K3/422 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4679 ,  H05K2201/09463 ,  H05K2201/09854 ,  H05K2203/0505

Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

Abstract translation: 光致抗蚀剂沉积在基底上的种子层上。 去除光致抗蚀剂的第一区域以暴露种子层的第一部分以形成通孔垫结构。 第一导电层沉积在种子层的第一部分上。 去除与第一区域相邻的光致抗蚀剂的第二区域以暴露种子层的第二部分以形成线。 第二导电层沉积在第一导电层和籽晶层的第二部分上。

公开(公告)号：US20250070083A1

公开(公告)日：2025-02-27

申请号：US18942054

申请日：2024-11-08

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20200235449A1

公开(公告)日：2020-07-23

申请号：US16841072

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H01P3/06 ,  H01P3/02 ,  H05K1/02 ,  H01P3/08

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20180328957A1

公开(公告)日：2018-11-15

申请号：US15771869

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Feras EID ,  Henning BRAUNISCH ,  Georgios C. DOGIAMIS ,  Sasha N. OSTER

IPC: G01P15/097 ,  B81B7/00 ,  B81C1/00 ,  G01P15/08

CPC classification number: G01P15/097 ,  B81B7/0006 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81B2203/04 ,  B81B2203/053 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00166 ,  B81C1/0023 ,  G01P15/0802

Abstract: Embodiments of the invention include a microelectronic device having a sensing device and methods of forming the sensing device. In an embodiment, the sensing device includes a mass and a plurality of beams to suspend the mass. Each beam comprises first and second conductive layers and an insulating layer positioned between the first and second conductive layers to electrically isolate the first and second conductive layers. The first conductive layer is associated with drive signals and the second conductive layer is associated with sense signals of the sensing device.