公开(公告)号：US20230138543A1

公开(公告)日：2023-05-04

申请号：US18091982

申请日：2022-12-30

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

摘要： Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20220344273A1

公开(公告)日：2022-10-27

申请号：US17861125

申请日：2022-07-08

申请人： Intel Corporation

发明人： Toshihiro TOMITA ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16

摘要： Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20200286834A1

公开(公告)日：2020-09-10

申请号：US16879318

申请日：2020-05-20

申请人： Intel Corporation

发明人： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16

摘要： Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20200036095A1

公开(公告)日：2020-01-30

申请号：US16465980

申请日：2017-01-04

申请人： Intel Corporation

发明人： Adel A. ELSHERBINI ,  Shawna M. LIFF ,  William J. LAMBERT

IPC分类号： H01Q3/34 ,  H01Q21/06 ,  H01Q21/00 ,  H04B1/02

摘要： Embodiments are generally directed to a package architecture for antenna arrays. An embodiment of an apparatus includes an electronic package, the electronic package including one or more routing layers; a transmitter to drive a signal for wireless transmission; and an assembled phased array antenna to transmit the signal, the assembled phased array antenna including a plurality of separate antenna elements in an array, each antenna element of the array being individually attached to a first side of the electronic package. The antenna elements include a first antenna element and a second antenna element, wherein the first antenna element is separated from the second antenna element by a gap.

公开(公告)号：US20190214338A1

公开(公告)日：2019-07-11

申请号：US16328231

申请日：2016-09-14

申请人： Intel Corporation

发明人： Eng Huat GOH ,  Jiun Hann SIR ,  Min Suet LIM ,  Shawna M. LIFF ,  Feras EID

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/00 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/552 ,  H01L23/562

摘要： Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.

公开(公告)号：US20190025573A1

公开(公告)日：2019-01-24

申请号：US16072164

申请日：2016-04-01

申请人： Intel Corporation

发明人： Aleksandar ALEKSOV ,  Feras EID ,  Sasha N. OSTER ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Thomas L. SOUNART ,  Baris BICEN ,  Valluri R. RAO

IPC分类号： G02B26/10 ,  G02B26/08

摘要： Embodiments of the invention include maskless imaging tools and display systems that include piezoelectrically actuated mirrors and methods of forming such devices. According to an embodiment, the maskless imaging tool may include a light source. Additionally, the tool may include one or more piezoelectrically actuated mirrors for receiving light from the light source. In an embodiment, the piezoelectrically actuated mirrors are actuatable about one or more axes to reflect the light from the light source to a workpiece positioned to receive light from the piezoelectrically actuated mirror. Additional embodiments of the invention may include a maskless imaging tool that is a laser direct imaging lithography (LDIL) tool. Other embodiments may include a maskless imaging tool that is a via-drill tool. Embodiments of the invention may also include a piezoelectrically actuated mirror used in a projection system. For example, the projection system may be integrated into a pair of glasses.

公开(公告)号：US20180358296A1

公开(公告)日：2018-12-13

申请号：US15778398

申请日：2015-12-22

申请人： INTEL CORPORATION

发明人： Eric J. LI ,  Nitin DESHPANDE ,  Shawna M. LIFF ,  Omkar KARHADE ,  Amram EITAN ,  Timothy A. GOSSELIN

IPC分类号： H01L23/538 ,  H01L23/367 ,  H01L21/48

CPC分类号： H01L23/5381 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/13 ,  H01L23/36 ,  H01L23/367 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2924/00014

摘要： An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

公开(公告)号：US20180097284A1

公开(公告)日：2018-04-05

申请号：US15283140

申请日：2016-09-30

申请人： Intel Corporation

发明人： Shawna M. LIFF ,  Adel A. ELSHERBINI ,  Sasha N. OSTER ,  Feras EID ,  Georgios C. DOGIAMIS ,  Thomas L. SOUNART ,  Johanna M. SWAN

IPC分类号： H01Q1/52 ,  H01L41/09 ,  H01L41/047 ,  H01L41/187 ,  H01L41/04 ,  H01Q5/50 ,  H04L29/06

CPC分类号： H01Q1/526 ,  H01L41/047 ,  H01L41/094 ,  H01Q1/273 ,  H01Q15/0086 ,  H04L63/0245 ,  H04L63/1475 ,  H04L67/12 ,  H04L67/146 ,  H04W12/0052 ,  H04W12/12

摘要： Embodiments of the invention include a reconfigurable communication system, that includes a substrate and a metamaterial shield formed over the substrate. In an embodiment, the metamaterial shield surrounds one or more components on the substrate. Additionally, a plurality of first piezoelectric actuators may be formed on the substrate. The first piezoelectric actuators may be configured to deform the metamaterial shield and change a frequency band that is permitted to pass through the metamaterial shield. Embodiments may also include a reconfigurable antenna that includes a metamaterial. In an embodiment, a plurality of second piezoelectric actuators may be configured to deform the metamaterial of the antenna and change a central operating frequency of the antenna. Embodiments may also include an integrated circuit electrically coupled to the plurality of first piezoelectric actuators and second piezoelectric actuators.

公开(公告)号：US20240355750A1

公开(公告)日：2024-10-24

申请号：US18758992

申请日：2024-06-28

申请人： Intel Corporation

发明人： Adel A. ELSHERBINI ,  Amr ELSHAZLY ,  Arun CHANDRASEKHAR ,  Shawna M. LIFF ,  Johanna M. SWAN

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/00 ,  H01L2224/16225 ,  H01L2224/1703

摘要： Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20230197520A1

公开(公告)日：2023-06-22

申请号：US17557579

申请日：2021-12-21

申请人： Intel Corporation

发明人： Yi SHI ,  Omkar KARHADE ,  Shawna M. LIFF ,  Zhihua ZOU ,  Ryan MACKIEWICZ ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Arnab SARKAR

IPC分类号： H01L21/822 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/822 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/15311

摘要： Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.