公开(公告)号：US20140281274A1

公开(公告)日：2014-09-18

申请号：US13844817

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Gilles A. Pokam ,  Rolf Kassa ,  Klaus Danne ,  Tim Kranich ,  Cristiano L. Pereira ,  Justin E. Gottschlich ,  Shiliang Hu

IPC: G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/321 ,  G06F12/0811 ,  G06F12/0842 ,  Y02B70/12 ,  Y02D10/13

Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.

Abstract translation: 一种用于在存在复杂多操作指令的情况下记录共享存储器访问的交错的系统，处理器和方法。 公开了对指令原子性（IA）的扩展，使得如果硬件已经记录了由于指令原子性违规（IAV）引起的依赖关系，则软件可以推断关于多操作执行的部分信息。 通过监视多操作指令的进度，不需要复杂的多操作仿真。

公开(公告)号：US20140223166A1

公开(公告)日：2014-08-07

申请号：US14169955

申请日：2014-01-31

Applicant: INTEL CORPORATION

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F9/445

CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract translation: 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

公开(公告)号：US20220326756A1

公开(公告)日：2022-10-13

申请号：US17852066

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core

公开(公告)号：US10437318B2

公开(公告)日：2019-10-08

申请号：US14986677

申请日：2016-01-02

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US10394561B2

公开(公告)日：2019-08-27

申请号：US15297885

申请日：2016-10-19

Applicant: INTEL CORPORATION

Inventor： Nathan D. Dautenhahn ,  Justin Gottschlich ,  Gilles Pokam ,  Cristiano Pereira ,  Shiliang Hu ,  Klaus Danne ,  Rolf Kassa

IPC: G06F9/45 ,  G06F9/30 ,  G06F11/07 ,  G06F9/38 ,  G06F11/14 ,  G06F11/36 ,  G06F9/52

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

公开(公告)号：US10120781B2

公开(公告)日：2018-11-06

申请号：US15026515

申请日：2013-12-12

Applicant: INTEL CORPORATION

Inventor： Shiliang Hu ,  Gilles A. Pokam ,  Cristiano L. Pereira ,  Justin E. Gottschlich

IPC: G06F9/44 ,  G06F9/45 ,  G06F11/36 ,  G06F9/52 ,  G06F11/30 ,  G06F11/34

Abstract: Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.

公开(公告)号：US20160019038A1

公开(公告)日：2016-01-21

申请号：US14867950

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Mauricio Breternitz, JR. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Criag B. Zilles

IPC: G06F9/45 ,  G06F11/36

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.