公开(公告)号：US20230350814A1

公开(公告)日：2023-11-02

申请号：US18078762

申请日：2022-12-09

Applicant: Intel Corporation

Inventor： Thomas Unterluggauer ,  Fangfei Liu ,  Carlos Rozas ,  Scott Constable ,  Gilles Pokam ,  Francis McKeen ,  Christopher Wilkerson ,  Erik Hallnor

IPC: G06F12/14 ,  G06F12/0815 ,  G06F12/121

CPC classification number: G06F12/1408 ,  G06F12/0815 ,  G06F12/121 ,  G06F2212/1052

Abstract: Techniques and mechanisms for a victim cache to operate in conjunction with another cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a primary cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the primary cache. The victim cache is accessed using an independently randomized mapping. Subsequently, a request to access the first line results in a search of the victim cache and the primary cache. Based on the search, the first line is evicted from the victim cache, and reinserted in the primary cache. In another embodiment, reinsertion of the first line in the primary cache includes the first line and a third line being swapped between the primary cache and the victim cache.

公开(公告)号：US20220100520A1

公开(公告)日：2022-03-31

申请号：US17033771

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Gilles Pokam ,  Jared Stark ,  Niranjan Kumar Soundararajan ,  Oleg Ladin

IPC: G06F9/38 ,  G06F12/0875

Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating frontend branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.

公开(公告)号：US20160224457A1

公开(公告)日：2016-08-04

申请号：US15096141

申请日：2016-04-11

Applicant: Intel Corporation

Inventor： Justin Gottschlich ,  Gilles Pokam ,  Cristiano Pereira ,  Jungwoo Ha

IPC: G06F11/36

CPC classification number: G06F11/3632 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/4881 ,  G06F11/3644 ,  G06F11/3648 ,  G06F11/366

Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.

Abstract translation: 公开了在多线程程序中识别和再现并发冲突的方法和系统。 本文公开的示例性方法包括确定是否满足条件并且相对于多线程程序的第二线程的操作来序列化多线程程序的第一线程的操作。 第一和第二个线程的操作的序列化导致并发冲突或错误，从而导致多线程程序崩溃。 以这种方式，会识别负责并发冲突的多线程程序的第一个和第二个线程的操作，并且可以修改以消除该错误。

公开(公告)号：US11928472B2

公开(公告)日：2024-03-12

申请号：US17033771

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Gilles Pokam ,  Jared Warner Stark, IV ,  Niranjan Kumar Soundararajan ,  Oleg Ladin

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3844 ,  G06F12/0875 ,  G06F9/30145 ,  G06F2212/452

Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating front-end branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220206819A1

公开(公告)日：2022-06-30

申请号：US17134335

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Gilles Pokam ,  Asit Mallick ,  Martin Dixon ,  Michael Chynoweth

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability mitigation hardware and speculation vulnerability detection hardware. The speculation vulnerability mitigation hardware is to implement one or more of a plurality of speculation vulnerability mitigation mechanisms. The speculation vulnerability detection hardware to detect vulnerability to a speculative execution attack and to provide to software an indication of speculative execution attack vulnerability.

公开(公告)号：US10394561B2

公开(公告)日：2019-08-27

申请号：US15297885

申请日：2016-10-19

Applicant: INTEL CORPORATION

Inventor： Nathan D. Dautenhahn ,  Justin Gottschlich ,  Gilles Pokam ,  Cristiano Pereira ,  Shiliang Hu ,  Klaus Danne ,  Rolf Kassa

IPC: G06F9/45 ,  G06F9/30 ,  G06F11/07 ,  G06F9/38 ,  G06F11/14 ,  G06F11/36 ,  G06F9/52

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

公开(公告)号：US20250103512A1

公开(公告)日：2025-03-27

申请号：US18474981

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Thomas Unterluggauer ,  Fangfei Liu ,  Scott D. Constable ,  Carlos V. Rozas ,  Gilles Pokam ,  Boris Dolgunov

IPC: G06F12/14 ,  G06F12/0808

Abstract: Techniques for cache scrubbing for cache-set randomization to resist contention-based cache attacks are described. In certain examples, a system includes a memory; an execution circuit to cause a memory access request for the memory; a cache to store a plurality of sets that each include a plurality of cache lines from the memory; a cache randomizer circuit to generate a randomized index into the plurality of sets of the cache based on an address of the memory access request; and a cache scrubber circuit to determine that a number of invalid cache lines in a set of the plurality of sets of the cache is less than a threshold number of invalid cache lines, and in response, invalidate a valid cache line in the set of the plurality of sets of the cache.

公开(公告)号：US10387296B2

公开(公告)日：2019-08-20

申请号：US14836103

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Justin Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano Pereira

IPC: G06F9/44 ,  G06F11/00 ,  G06F9/46 ,  G06F11/36 ,  G06F8/70 ,  G06F8/41 ,  G06F9/448

Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

公开(公告)号：US20150363306A1

公开(公告)日：2015-12-17

申请号：US14836103

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Justin Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai

IPC: G06F11/36 ,  G06F9/44

CPC classification number: G06F11/3688 ,  G06F8/434 ,  G06F8/70 ,  G06F9/448 ,  G06F11/36 ,  G06F11/3604 ,  G06F11/3612 ,  G06F11/3632 ,  G06F11/3636 ,  G06F11/3672

Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

Abstract translation: 公开了用于识别负责在具有多个同时执行的线程的计算机程序中引起并发错误的线程的方法和系统。 本文公开的示例性方法包括使用处理器来定义数据类型。 所述数据类型包括第一谓词，使用插入在所述多个线程的第一线程中的第一程序指令来调用所述第一谓词，第二谓词，所述第二谓词使用插入到所述第一线索的第二线程中的第二程序指令来调用 多个线程，以及定义第一谓词和第二谓词之间的关系的表达式。 该方法还包括响应于确定在执行计算机程序期间的关系得到满足，识别第一线程和第二线程，以负责并发错误。

公开(公告)号：US20150363242A1

公开(公告)日：2015-12-17

申请号：US14833315

申请日：2015-08-24

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F11/3632

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.

Abstract translation: 公开了方法，装置，系统和制品以管理并发谓词表达。 一种示例性方法公开了将第一条件钩插入到第一线程中，与第一条件相关联的第一条件钩，将第二条件钩插入到第二线程中，与第二条件相关联的第二条件钩，防止第二线程执行 直到满足第一条件，并且当满足第二条件时识别并发冲突。