公开(公告)号：US20190198093A1

公开(公告)日：2019-06-27

申请号：US16226385

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/419 ,  G11C11/412

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

公开(公告)号：US10298117B2

公开(公告)日：2019-05-21

申请号：US15638643

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Harish Krishnamurthy ,  Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H04W84/20 ,  H02M1/42 ,  H03M1/00 ,  H02M1/00 ,  H02M1/084 ,  H02M3/158

Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

公开(公告)号：US20190043477A1

公开(公告)日：2019-02-07

申请号：US16022376

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Muhammad Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Wootaek Lim ,  Tobias Bocklet ,  David Pearce

IPC: G10L15/02

Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.

公开(公告)号：US20180375433A1

公开(公告)日：2018-12-27

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/1582 ,  G05F1/67 ,  H02M1/08 ,  H02M2001/0003 ,  H02M2001/0009 ,  H02M2001/0025

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.