公开(公告)号：US20180196727A1

公开(公告)日：2018-07-12

申请号：US15402412

申请日：2017-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. GIAMEI ,  Christian JACOBI ,  Daniel V. ROSA ,  Anthony SAPORITO ,  Donald W. SCHMIDT

IPC: G06F11/34 ,  G06F9/48 ,  G06F11/30

CPC classification number: G06F11/3433 ,  G06F9/4881 ,  G06F9/5033 ,  G06F11/3024 ,  G06F11/3419 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2209/508

Abstract: A facility is provided for collecting time-slice-instrumentation information during processing unit execution. The facility counts, at least in part, occurrence of a specified processing unit event during a time-slice of processing unit execution. The counted events occurring during a first interval of execution and a second interval of execution of the time-slice are retained. The first interval of execution is earlier in the time-slice than the second interval of execution, and the counted events facilitate adjusting performance of the processing unit. In an embodiment, the time-slice is a contiguous period of time of processing unit execution, and the specified processing unit event includes a cache event. The processing unit may interleave processing of multiple different units of work across multiple contiguous time-slices, and during a single time-slice, a single unit of work of the multiple different units of work is processed by the processing unit.

公开(公告)号：US20160202978A1

公开(公告)日：2016-07-14

申请号：US14995358

申请日：2016-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. BRADBURY ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Eric M. SCHWARZ ,  Timothy J. SLEGEL

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/45516

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.

公开(公告)号：US20210096998A1

公开(公告)日：2021-04-01

申请号：US17117299

申请日：2020-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. GIAMEI ,  Christian JACOBI ,  Daniel V. ROSA ,  Anthony SAPORITO ,  Donald W. SCHMIDT ,  Chung-Lung K. SHUM

IPC: G06F12/0875 ,  G06F12/1027 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0815 ,  G06F12/084 ,  G06F9/30 ,  G06F9/38

Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.

公开(公告)号：US20200159670A1

公开(公告)日：2020-05-21

申请号：US16752754

申请日：2020-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/455

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US20180260337A1

公开(公告)日：2018-09-13

申请号：US15798585

申请日：2017-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US20180196754A1

公开(公告)日：2018-07-12

申请号：US15404254

申请日：2017-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. GIAMEI ,  Christian JACOBI ,  Daniel V. ROSA ,  Anthony SAPORITO ,  Donald W. SCHMIDT ,  Chung-Lung K. SHUM

IPC: G06F12/0875 ,  G06F12/1027 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0815 ,  G06F12/084

Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

公开(公告)号：US20170192800A1

公开(公告)日：2017-07-06

申请号：US15289513

申请日：2016-10-10

Applicant: International Business Machines Corporation

Inventor： Giles R. FRAZIER ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Chung-Lung K. SHUM

IPC: G06F9/445 ,  G06F9/45

CPC classification number: G06F11/3636 ,  G06F8/41 ,  G06F9/44589 ,  G06F11/0706 ,  G06F11/0751 ,  G06F11/3688

Abstract: A method, computer program product, and system performing a method that include a processor defining a code fingerprint by obtaining parameters describing at least one of an event type or an event. The code fingerprint includes a first sequence. The processor loads the code fingerprint into a register accessible to the processor. Concurrent with executing a program, the processor obtains the code fingerprint from the register and identifies the code fingerprint in the program by comparing a second sequence in the program to the first sequence. Based on identifying the code fingerprint in the program, the processor alerts a runtime environment where the program is executing.

公开(公告)号：US20170192757A1

公开(公告)日：2017-07-06

申请号：US15210703

申请日：2016-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Giles R. FRAZIER ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Chung-Lung K. SHUM

IPC: G06F9/45

CPC classification number: G06F8/41 ,  G06F9/44589 ,  G06F17/5054

Abstract: A method, computer program product, and system performing a method that includes a processor compiling a description including information to be utilized by programmable logic to recognize a code fingerprint in a program executing in the runtime environment. The method also includes the processor configuring the programmable logic, by loading the description into the programmable logic at a predefined time and obtaining, during runtime of the program, an alert that the programmable logic recognized the code fingerprint in the program.

公开(公告)号：US20170161362A1

公开(公告)日：2017-06-08

申请号：US14958493

申请日：2015-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. BRADBURY ,  Markus HELMS ,  Christian JACOBI ,  Aditya N. PURANIK ,  Christian ZOELLIN

IPC: G06F17/30 ,  G06F3/06

CPC classification number: G06F17/2705 ,  G06F3/0608 ,  G06F3/0626 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F17/30371 ,  G06F17/30961 ,  H03M7/3079 ,  H03M7/3088 ,  H03M7/40

Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

公开(公告)号：US20160266903A1

公开(公告)日：2016-09-15

申请号：US15163161

申请日：2016-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. BRADBURY ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Eric M. SCHWARZ ,  Timothy J. SLEGEL

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3824 ,  G06F12/0875 ,  G06F2212/452

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.