公开(公告)号：US20230054424A1

公开(公告)日：2023-02-23

申请号：US17407248

申请日：2021-08-20

Applicant: International Business Machines Corporation

Inventor： Ram Sai Manoj BAMDHAMRAVURI ,  Craig R. WALTERS ,  Christian JACOBI ,  Timothy BRONSON ,  Gregory William ALEXANDER ,  Hieu T. HUYNH ,  Robert J. SONNELITTER, III ,  Jason D. KOHL ,  Deanna P. D. BERGER ,  Richard Joseph BRANCIFORTE

IPC: G06F12/0891 ,  G06F12/0895 ,  G06F12/123

Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

公开(公告)号：US20180349274A1

公开(公告)日：2018-12-06

申请号：US15820635

申请日：2017-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Giles R. FRAZIER ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Younes MANTON ,  Anthony SAPORITO ,  Chung-Lung K. SHUM

IPC: G06F12/02 ,  G06F12/0802

CPC classification number: G06F12/0261 ,  G06F12/0802 ,  G06F2212/1044

Abstract: A garbage collection facility is provided for memory management within a computer. The facility implements, in part, grouping of infrequently accessed data units in a designated transient memory area, and includes designating an area of the memory as a transient memory area and an area as a conventional memory area, and counting, for each data unit in the transient or conventional memory areas a number of accesses to the data unit. The counting provides a respective access count for each data unit. For each data unit in the transient memory area or the conventional memory area, a determination is made whether the respective access count is below a transient threshold ascertained to separate frequently accessed data units and infrequently used data units. Data units with respective access counts below the transient threshold are grouped together as transient data units within the transient memory area.

公开(公告)号：US20160266904A1

公开(公告)日：2016-09-15

申请号：US15163348

申请日：2016-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. BRADBURY ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Eric M. SCHWARZ ,  Timothy J. SLEGEL

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3824 ,  G06F12/0875 ,  G06F2212/452

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.

公开(公告)号：US20130318330A1

公开(公告)日：2013-11-28

申请号：US13953303

申请日：2013-07-29

Applicant: International Business Machines Corporation

Inventor： Gregory W. ALEXANDER ,  Khary J. ALEXANDER ,  Brian CURRAN ,  Jonathan T. HSIEH ,  Christian JACOBI ,  James R. MITCHELL ,  Brian R. PRASKY ,  Brian W. THOMPTO

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838

Abstract: A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag, the load instruction becomes dependent upon all store instructions associated with a substantially similar hazard indicating flag.

Abstract translation: 一种方法和信息处理系统管理可以执行无序的加载和存储操作。 执行加载指令和存储指令中的至少一个。 确定已经遇到操作数存储比较危险。 基于确定，创建操作数存储中的条目比较危险预测表。 该条目至少包括已执行的指令的指令地址和与指令相关联的危险指示标志。 危险指示标志表示该指令遇到操作数存储比较危险。 当加载指令与危险指示标志相关联时，加载指令取决于与基本相似的危险指示标志相关联的所有存储指令。

公开(公告)号：US20190243709A1

公开(公告)日：2019-08-08

申请号：US16386577

申请日：2019-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick J. MEANEY ,  Christian JACOBI ,  Barry M. TRAGER

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/09 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G06F11/108 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/1515

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols for the memory modules. A host receives and decodes the ECC symbols and executes error correction operations. The host and the memory modules are coupled by a number of channels.

公开(公告)号：US20190163565A1

公开(公告)日：2019-05-30

申请号：US15827285

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick J. MEANEY ,  Christian JACOBI ,  Barry M. TRAGER

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  H03M13/09

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.

公开(公告)号：US20180349273A1

公开(公告)日：2018-12-06

申请号：US15609469

申请日：2017-05-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Giles R. FRAZIER ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Younes MANTON ,  Anthony SAPORITO ,  Chung-Lung K. SHUM

IPC: G06F12/02 ,  G06F12/0802

CPC classification number: G06F12/0261 ,  G06F12/0802 ,  G06F2212/1044

Abstract: A garbage collection facility is provided for memory management within a computer. The facility implements, in part, grouping of infrequently accessed data units in a designated transient memory area, and includes designating an area of the memory as a transient memory area and an area as a conventional memory area, and counting, for each data unit in the transient or conventional memory areas a number of accesses to the data unit. The counting provides a respective access count for each data unit. For each data unit in the transient memory area or the conventional memory area, a determination is made whether the respective access count is below a transient threshold ascertained to separate frequently accessed data units and infrequently used data units. Data units with respective access counts below the transient threshold are grouped together as transient data units within the transient memory area.

公开(公告)号：US20180196751A1

公开(公告)日：2018-07-12

申请号：US15404247

申请日：2017-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. GIAMEI ,  Christian JACOBI ,  Daniel V. ROSA ,  Anthony SAPORITO ,  Donald W. SCHMIDT ,  Chung-Lung K. SHUM

IPC: G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/6042

Abstract: A computing environment facility is provided to extend a hold of a cache line in private (or local) cache exclusively after processing a storage operand request. The facility includes determining whether a storage operand request to a storage location shared by multiple processing units of the computing environment is designated hold. In addition, a determination is made whether a state of the corresponding cache line in private cache used for processing the storage operand request is owned exclusively. Based on determining that the storage operand request is designated hold, and that the state of the corresponding cache line in private cache used for processing the storage operand request is owned exclusively, continuing to hold the corresponding cache line in the private cache exclusively after completing processing of the storage operand request. The continuing to hold may include initiating a counter to facilitate the continuing hold for a desired, set interval.

公开(公告)号：US20180074826A1

公开(公告)日：2018-03-15

申请号：US15802725

申请日：2017-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. GSCHWIND ,  Christian JACOBI ,  Anthony SAPORITO ,  Chung-Lung K. SHUM

IPC: G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/3802 ,  G06F9/30047 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.

公开(公告)号：US20190391922A1

公开(公告)日：2019-12-26

申请号：US16561352

申请日：2019-09-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. GIAMEI ,  Christian JACOBI ,  Daniel V. ROSA ,  Anthony SAPORITO ,  Donald W. SCHMIDT ,  Chung-Lung K. SHUM

IPC: G06F12/0875 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/1027

Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.