公开(公告)号：US09886350B2

公开(公告)日：2018-02-06

申请号：US15048281

申请日：2016-02-19

Applicant: International Business Machines Corporation

Inventor： Guy Lynn Guthrie ,  Naresh Nayar ,  Geraint North ,  Hugh Shen ,  William Starke ,  Phillip Williams

IPC: G06F9/455 ,  G06F11/14 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0891 ,  G06F12/0804

CPC classification number: G06F11/1451 ,  G06F9/45533 ,  G06F9/45558 ,  G06F11/1438 ,  G06F11/1458 ,  G06F11/1484 ,  G06F12/0804 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0895 ,  G06F2009/45583 ,  G06F2201/805 ,  G06F2201/815 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/60

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

公开(公告)号：US20170068545A1

公开(公告)日：2017-03-09

申请号：US14848516

申请日：2015-09-09

Applicant: International Business Machines Corporation

Inventor： Benjamin Carter Nowak ,  Guy Lynn Guthrie ,  Venkat R. Indukuru

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0815

Abstract: A hint bit detection and correction method and system that uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.

Abstract translation: 提示位检测和校正方法和系统，其使用两个附加位作为每个缓存目录的一部分。 这些位表示lwarx和stwcx指令（larx disp，stcx disp）。 当出现提示位事件时，根据这两个位的组合，可能会显示一个提示位错误。 一旦检测到提示位错误，就会发出软件中断，提示位校正方法识别和纠正不正确的提示位。

公开(公告)号：US20150127909A1

公开(公告)日：2015-05-07

申请号：US14170106

申请日：2014-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016

Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.

Abstract translation: 用于操作高可用性（HA）数据处理系统的技术包括响应于在高速缓存处接收到HA注销指示，启动高速缓存行走以定位包括HA数据的高速缓存中的高速缓存行。 响应于确定高速缓存行包括HA数据，高速缓存行的地址被记录在高速缓存中的缓冲器的第一部分中。 响应于缓冲器的第一部分达到确定的填充级别，缓冲器的第一部分的内容被记录到另一个存储器。 响应缓存中的所有缓存行被行走，高速缓存行走终止。

公开(公告)号：US20150100731A1

公开(公告)日：2015-04-09

申请号：US14048474

申请日：2013-10-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy Lynn Guthrie ,  Steven R. Kunkel ,  Hien Minh Le ,  Geraint North ,  William J. Starke

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0802 ,  G06F11/1405 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/152

Abstract: A technique of operating a data processing system, includes logging addresses for cache lines modified by a producer core in a data array of a producer cache to create a high-availability (HA) log for the producer core. The technique also includes moving the HA log directly from the producer cache to a consumer cache of a consumer core and moving HA data associated with the addresses of the HA log directly from the producer cache to the consumer cache. The HA log corresponds to a cache line that includes multiple of the addresses. Finally, the technique includes processing, by the consumer core, the HA log and the HA data for the data processing system.

Abstract translation: 操作数据处理系统的技术包括记录由生产者高速缓存的数据阵列中的生产者核心修改的高速缓存行的地址，以为生产者核心创建高可用性（HA）日志。 该技术还包括将HA日志从生产者缓存直接移动到消费者核心的消费者缓存，并将与HA日志的地址相关联的HA数据直接从生产者缓存移动到消费者缓存。 HA日志对应于包含多个地址的高速缓存行。 最后，该技术包括消费者核心处理数据处理系统的HA日志和HA数据。