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公开(公告)号：US10224273B2
公开(公告)日：2019-03-05
申请号：US15796770
申请日：2017-10-28
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof
IPC: H01L23/00 , H01L23/50 , H01L25/18 , H01L23/367 , H01L23/498 , H01L23/522
Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.
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公开(公告)号：US20180012838A1
公开(公告)日：2018-01-11
申请号：US15207077
申请日：2016-07-11
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof
IPC: H01L23/522 , H01L23/00
CPC classification number: H01L23/5223 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/50 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/81 , H01L2224/16225 , H01L2224/73253 , H01L2224/81815 , H01L2924/15311 , H01L2924/16152 , H01L2924/19103
Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc. includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.
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公开(公告)号：US09553079B1
公开(公告)日：2017-01-24
申请号：US14969765
申请日：2015-12-15
Applicant: International Business Machines Corporation
Inventor： Jean Audet , Luc G. Guerin , Richard Langlois , Stephan L. Martel , Sylvain E. Ouimet
CPC classification number: H01L24/08 , H01L23/49816 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/73 , H01L24/81 , H01L25/16 , H01L28/40 , H01L2224/0401 , H01L2224/08265 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2224/16265 , H01L2224/1703 , H01L2224/17051 , H01L2224/73201 , H01L2224/73204 , H01L2224/80815 , H01L2224/81191 , H01L2224/81192 , H01L2224/81815 , H01L2224/81986 , H01L2224/92125 , H01L2924/15151 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/00014 , H01L2924/014
Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.
Abstract translation: 公开了一种倒装芯片组件，其包括具有管芯电路的管芯和电连接到管芯电路的多个电触点。 衬底包括与相应的管芯电触头并置并电连接的电触头。 无源部件设置在管芯和衬底之间，并且包括设置在第一电极和第二电极之间的电介质。 第一电极电连接到第一管芯电触点和对应的衬底电接触，并且第二电极电连接到第二管芯电触点和相应的衬底电接触。
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公开(公告)号：US10784202B2
公开(公告)日：2020-09-22
申请号：US15828463
申请日：2017-12-01
Applicant: International Business Machines Corporation
Inventor： Francois Arguin , Luc Guerin , Maryse Cournoyer , Steve E. Whitehead , Jean Audet , Richard D. Langlois , Christian Bergeron , Pascale Gagnon , Nathalie Meunier
IPC: H01L23/538 , H01L25/18 , H01L23/498 , H01L25/065 , H01L23/00
Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.
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公开(公告)号：US10706204B2
公开(公告)日：2020-07-07
申请号：US16149313
申请日：2018-10-02
Applicant: International Business Machines Corporation
Inventor： Jean Audet , Alain Ayotte , Franklin Baez , Anson Call , Deana Cosmadelis , Jason Lee Frankel , Kevin Grosselfinger , Roxan Lemire , Marek Andrzej Orlowski , Gilles Poitras , Paul Robert Walling
IPC: G06F30/398 , G06F30/392
Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.
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Patent Agency Ranking
公开(公告)号：US10660209B2
公开(公告)日：2020-05-19
申请号：US15811852
申请日：2017-11-14
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Brian W. Quinlan , Charles L. Reynolds , Jean Audet , Francesco Preda
Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.
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27.发明申请公开(公告)号：US20190172784A1
公开(公告)日：2019-06-06
申请号：US16269730
申请日：2019-02-07
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof
IPC: H01L23/522 , H01L23/498 , H01L23/50 , H01L23/00
Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.
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公开(公告)号：US20190150287A1
公开(公告)日：2019-05-16
申请号：US15811852
申请日：2017-11-14
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Brian W. Quinlan , Charles L. Reynolds , Jean Audet , Francesco Preda
Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.
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公开(公告)号：US09984988B2
公开(公告)日：2018-05-29
申请号：US15396845
申请日：2017-01-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Jean Audet , Luc G. Guerin , Richard Langlois , Stephan L. Martel , Sylvain E. Ouimet
CPC classification number: H01L24/08 , H01L23/49816 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/73 , H01L24/81 , H01L25/16 , H01L28/40 , H01L2224/0401 , H01L2224/08265 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2224/16265 , H01L2224/1703 , H01L2224/17051 , H01L2224/73201 , H01L2224/73204 , H01L2224/80815 , H01L2224/81191 , H01L2224/81192 , H01L2224/81815 , H01L2224/81986 , H01L2224/92125 , H01L2924/15151 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/00014 , H01L2924/014
Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.
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30.发明申请公开(公告)号：US20180068945A1
公开(公告)日：2018-03-08
申请号：US15796782
申请日：2017-10-28
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof
IPC: H01L23/522 , H01L23/00
CPC classification number: H01L23/5223 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/50 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/18 , H01L2224/13101 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2924/15311 , H01L2924/16152 , H01L2924/19103 , H01L2924/19107 , H01L2924/014 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.
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