公开(公告)号：US20200052181A1

公开(公告)日：2020-02-13

申请号：US16597604

申请日：2019-10-09

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L39/02 ,  G06N10/00 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L39/22 ,  H01L39/24 ,  H03K19/195 ,  H01L27/18

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

公开(公告)号：US10446736B2

公开(公告)日：2019-10-15

申请号：US15822338

申请日：2017-11-27

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/108 ,  H01L39/02 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3205 ,  H01L39/22 ,  H03K19/195 ,  H01L39/24 ,  G06N10/00

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

公开(公告)号：US20190181325A1

公开(公告)日：2019-06-13

申请号：US16267463

申请日：2019-02-05

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/24 ,  H03K19/195 ,  H01L21/768 ,  H01L23/48 ,  H01L39/22 ,  H01L21/3205 ,  H01L23/532

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

公开(公告)号：US20190130302A1

公开(公告)日：2019-05-02

申请号：US16020902

申请日：2018-06-27

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Werner A. Rausch ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: G06N99/00 ,  H01G4/008 ,  H01L39/24 ,  H01L39/22 ,  H01L39/02 ,  H01L27/18

CPC classification number: G06N10/00 ,  H01G4/008 ,  H01L27/18 ,  H01L28/90 ,  H01L39/025 ,  H01L39/223 ,  H01L39/2406 ,  H01L39/2409

Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

公开(公告)号：US10170474B2

公开(公告)日：2019-01-01

申请号：US15862976

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/82 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/165 ,  H01L29/16 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

公开(公告)号：US10142335B2

公开(公告)日：2018-11-27

申请号：US14975512

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Chandrasekharan Kothandaraman ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H04L29/06

Abstract: An apparatus, method, system, and program product are disclosed for intrinsic chip identification. One method includes receiving first counter information from a device, determining whether such information matches second counter information, receiving first frequencies from the device, determining whether each frequency of such frequencies is within a predetermined range of a corresponding frequency of second frequencies, receiving a response to a challenge sent to the device, determining whether the response matches an expected response, and granting authentication. Granting authentication may include granting authentication in response to: the first counter information matching the second counter information; each frequency of the first frequencies being within the predetermined range of a corresponding frequency of the second frequencies; and the expected response matching the response. The expected response may be updated over time. The security apparatus may include circuitry that is shared with circuitry outside the security apparatus for computations other than authentication.

公开(公告)号：US20170277823A1

公开(公告)日：2017-09-28

申请号：US15619004

申请日：2017-06-09

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  G03F7/20 ,  H01L21/311 ,  H01L21/67 ,  H01L21/768

CPC classification number: G06F17/5081 ,  G03F7/2022 ,  G06F17/5077 ,  H01L21/31144 ,  H01L21/67063 ,  H01L21/76802 ,  H01L21/76816

Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

公开(公告)号：US20170180369A1

公开(公告)日：2017-06-22

申请号：US14975512

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Chandrasekharan Kothandaraman ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H04L29/06

CPC classification number: H04L63/0876

Abstract: An apparatus, method, system, and program product are disclosed for intrinsic chip identification. One method includes receiving first counter information from a device, determining whether such information matches second counter information, receiving first frequencies from the device, determining whether each frequency of such frequencies is within a predetermined range of a corresponding frequency of second frequencies, receiving a response to a challenge sent to the device, determining whether the response matches an expected response, and granting authentication. Granting authentication may include granting authentication in response to: the first counter information matching the second counter information; each frequency of the first frequencies being within the predetermined range of a corresponding frequency of the second frequencies; and the expected response matching the response. The expected response may be updated over time. The security apparatus may include circuitry that is shared with circuitry outside the security apparatus for computations other than authentication.

公开(公告)号：US20160027687A1

公开(公告)日：2016-01-28

申请号：US14873824

申请日：2015-10-02

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Abstract translation: 提供了一种设计布局，使得下面的导线结构位于上覆导电线结构中的针脚区域的下面。 当硬掩模层中的针脚区域被多次蚀刻时，可以在下面的导电线结构和上覆导电线结构之间形成针迹引导的通孔结构。 底层导线结构和上覆导线结构中的至少一个在相同设计级别上与其它导线结构电隔离，以避免无意的电短路。

公开(公告)号：US20150143305A1

公开(公告)日：2015-05-21

申请号：US14083578

申请日：2013-11-19

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Ian P. Stobert ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  H01L21/66

CPC classification number: G06F17/5068 ,  G03F9/7026 ,  H01L22/12 ,  H01L22/20

Abstract: A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions.

Abstract translation: 提供了在晶片表面的光刻曝光期间确定焦平面的方法。 该方法可以包括接收对应于晶片表面的表面形貌的数据，并且基于与表面形貌对应的接收数据，确定具有基本上不同的拓扑图的多个区域。 接收掩模版设计数据以在晶片表面上曝光，由此，从接收到的掩模版设计数据生成分配给所确定的多个区域中的相应一个的掩模版设计数据子集。 然后为确定的多个区域中的每一个生成最佳拟合焦平面。