Dynamic intrinsic chip identification

    公开(公告)号:US10142335B2

    公开(公告)日:2018-11-27

    申请号:US14975512

    申请日:2015-12-18

    Abstract: An apparatus, method, system, and program product are disclosed for intrinsic chip identification. One method includes receiving first counter information from a device, determining whether such information matches second counter information, receiving first frequencies from the device, determining whether each frequency of such frequencies is within a predetermined range of a corresponding frequency of second frequencies, receiving a response to a challenge sent to the device, determining whether the response matches an expected response, and granting authentication. Granting authentication may include granting authentication in response to: the first counter information matching the second counter information; each frequency of the first frequencies being within the predetermined range of a corresponding frequency of the second frequencies; and the expected response matching the response. The expected response may be updated over time. The security apparatus may include circuitry that is shared with circuitry outside the security apparatus for computations other than authentication.

    DYNAMIC INTRINSIC CHIP IDENTIFICATION
    28.
    发明申请

    公开(公告)号:US20170180369A1

    公开(公告)日:2017-06-22

    申请号:US14975512

    申请日:2015-12-18

    CPC classification number: H04L63/0876

    Abstract: An apparatus, method, system, and program product are disclosed for intrinsic chip identification. One method includes receiving first counter information from a device, determining whether such information matches second counter information, receiving first frequencies from the device, determining whether each frequency of such frequencies is within a predetermined range of a corresponding frequency of second frequencies, receiving a response to a challenge sent to the device, determining whether the response matches an expected response, and granting authentication. Granting authentication may include granting authentication in response to: the first counter information matching the second counter information; each frequency of the first frequencies being within the predetermined range of a corresponding frequency of the second frequencies; and the expected response matching the response. The expected response may be updated over time. The security apparatus may include circuitry that is shared with circuitry outside the security apparatus for computations other than authentication.

    INTERCONNECT LEVEL STRUCTURES FOR CONFINING STITCH-INDUCED VIA STRUCTURES
    29.
    发明申请
    INTERCONNECT LEVEL STRUCTURES FOR CONFINING STITCH-INDUCED VIA STRUCTURES 有权
    用于通过结构形成结构的互连水平结构

    公开(公告)号:US20160027687A1

    公开(公告)日:2016-01-28

    申请号:US14873824

    申请日:2015-10-02

    Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

    Abstract translation: 提供了一种设计布局,使得下面的导线结构位于上覆导电线结构中的针脚区域的下面。 当硬掩模层中的针脚区域被多次蚀刻时,可以在下面的导电线结构和上覆导电线结构之间形成针迹引导的通孔结构。 底层导线结构和上覆导线结构中的至少一个在相同设计级别上与其它导线结构电隔离,以避免无意的电短路。

    RETICLE DATA DECOMPOSITION FOR FOCAL PLANE DETERMINATION IN LITHOGRAPHIC PROCESSES
    30.
    发明申请
    RETICLE DATA DECOMPOSITION FOR FOCAL PLANE DETERMINATION IN LITHOGRAPHIC PROCESSES 有权
    用于在光刻过程中进行正交平面测定的数据分解

    公开(公告)号:US20150143305A1

    公开(公告)日:2015-05-21

    申请号:US14083578

    申请日:2013-11-19

    CPC classification number: G06F17/5068 G03F9/7026 H01L22/12 H01L22/20

    Abstract: A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions.

    Abstract translation: 提供了在晶片表面的光刻曝光期间确定焦平面的方法。 该方法可以包括接收对应于晶片表面的表面形貌的数据,并且基于与表面形貌对应的接收数据,确定具有基本上不同的拓扑图的多个区域。 接收掩模版设计数据以在晶片表面上曝光,由此,从接收到的掩模版设计数据生成分配给所确定的多个区域中的相应一个的掩模版设计数据子集。 然后为确定的多个区域中的每一个生成最佳拟合焦平面。

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