公开(公告)号：US20250062190A1

公开(公告)日：2025-02-20

申请号：US18451952

申请日：2023-08-18

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Jay William Strane ,  Shay Reboh ,  Brent A. Anderson ,  Junli Wang ,  Albert M. Chu

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

公开(公告)号：US11515392B2

公开(公告)日：2022-11-29

申请号：US17362369

申请日：2021-06-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  International Business Machines Corporation

Inventor： Shay Reboh ,  Remi Coquand ,  Nicolas Loubet ,  Tenko Yamashita ,  Jingyun Zhang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/76 ,  H01L29/775

Abstract: An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.

公开(公告)号：US11450755B2

公开(公告)日：2022-09-20

申请号：US16904138

申请日：2020-06-17

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shay Reboh ,  Emmanuel Augendre ,  Remi Coquand ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: An electronic device is provided, including a transistor and a substrate surmounted by first through third elements, the second element being arranged between the first and the third elements and including a nano-object, a transistor channel area being formed by part of the nano-object, a first end of the nano-object being connected to the first element by a first electrode including a first part forming a first continuity of matter and a second part formed on the first part, a second end of the nano-object being connected to the third element by a second electrode including a first part forming a second continuity of matter and a second part formed on the first part, such that a lattice parameter of the second part is suited to a lattice parameter of the first part to induce a stress in the nano-object along a reference axis.

公开(公告)号：US10818775B2

公开(公告)日：2020-10-27

申请号：US16190747

申请日：2018-11-14

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  International Business Machines Corporation

Inventor： Shay Reboh ,  Emmanuel Augendre ,  Remi Coquand ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L21/02 ,  H01L29/10 ,  H01L29/161 ,  H01L29/417 ,  H01L29/78

Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.

公开(公告)号：US10727320B2

公开(公告)日：2020-07-28

申请号：US15858266

申请日：2017-12-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shay Reboh ,  Emmanuel Augendre ,  Remi Coquand ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: A method of manufacturing a field effect transistor is provided, including supplying a substrate surmounted by first, second, and third structures, the second structure arranged between the first and the third structures and including at least one first nano-object located away from the substrate, a part of the first nano-object being configured to form a channel area of the transistor; forming electrodes of the transistor including epitaxial growth of a first material to obtain a first continuity of matter made of the first material between the second structure and the first structure, and to obtain a second continuity of matter made of the first material between the second structure and the third structure; and epitaxial growth of a second material, starting from the first material, the second material having a lattice parameter different from a lattice parameter of the first material of the first and the second continuities.

公开(公告)号：US20190051744A1

公开(公告)日：2019-02-14

申请号：US16054524

申请日：2018-08-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Remi Coquand ,  Nicolas Loubet ,  Shay Reboh ,  Robin Chao

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/7834 ,  H01L29/7842

Abstract: Fabrication of a microelectronic device comprising a semiconductor structure provided with semiconductor bars positioned above one another, the method comprising the following steps: creating, on a substrate, a stacked structure comprising an alternation of first bars containing a first material and having a first critical dimension and second bars (142, 144, 146) containing a second material, the second material being a semiconductor, the second bars having a second critical dimension greater than the first critical dimension, then, surface doping protruding lateral portions (15) of the second bars before formation of a source and drain block on these portions.

公开(公告)号：US20180175194A1

公开(公告)日：2018-06-21

申请号：US15837281

申请日：2017-12-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shay Reboh ,  Emmanuel Augendre ,  Remi Coquand ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/7842 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/78696

Abstract: A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a substrate and a layer of a first semiconductor, which is crystalline, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a nanowire stack, b) making a dummy gate and outer spacers, covering a part of the nanowire stack which is formed by portions of the nanowires, c) etching the nanowire stack such that only said part of the stack is preserved, d) removing the portion of the second semiconductor nanowire, e) depositing, in a space formed by this removal, a sacrificial material portion, f) making source and drain regions and inner spacers, g) removing the dummy gate and the sacrificial material portion, h) making a gate.