公开(公告)号：US10475911B2

公开(公告)日：2019-11-12

申请号：US16254235

申请日：2019-01-22

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Philip Christoph Brandt ,  Andre Rainer Stegner

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/167 ,  H01L21/22 ,  H01L21/24 ,  H01L21/266 ,  H01L29/18 ,  H01L21/265 ,  H01L29/45 ,  H01L29/06

Abstract: Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 1×1013 cm−3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 1×1014 cm−3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.

公开(公告)号：US10205011B2

公开(公告)日：2019-02-12

申请号：US15043084

申请日：2016-02-12

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Philip Christoph Brandt ,  Andre Rainer Stegner

IPC: H01L21/265 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/167 ,  H01L21/22 ,  H01L21/24 ,  H01L21/266 ,  H01L29/45 ,  H01L29/06

Abstract: Some embodiments relate to a method for forming a semiconductor device. The method includes forming a source region of a field effect transistor structure in a semiconductor substrate. The method further includes forming an oxide layer. The method also includes incorporating atoms of at least one atom type of a group of atom types into at least a part of the source region of the field effect transistor structure after forming the oxide layer. The group of atom types includes chalcogen atoms, silicon atoms and argon atoms.

公开(公告)号：US09685504B2

公开(公告)日：2017-06-20

申请号：US15253070

申请日：2016-08-31

Applicant: Infineon Technologies AG

Inventor： Andreas Haertl ,  Frank Hille ,  Francisco Javier Santos Rodriguez ,  Daniel Schloegl ,  Andre Rainer Stegner ,  Christoph Weiss

IPC: H01L29/00 ,  H01L21/22 ,  H01L21/38 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/32 ,  H01L21/285 ,  H01L29/167 ,  H01L29/861 ,  H01L21/265

CPC classification number: H01L29/063 ,  H01L21/26506 ,  H01L21/28568 ,  H01L29/0607 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/36 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66136 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66674 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/861

Abstract: A semiconductor device includes a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing lifetime and/or mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.

公开(公告)号：US20160372539A1

公开(公告)日：2016-12-22

申请号：US15253070

申请日：2016-08-31

Applicant: Infineon Technologies AG

Inventor： Andreas Haertl ,  Frank Hille ,  Francisco Javier Santos Rodriguez ,  Daniel Schloegl ,  Andre Rainer Stegner ,  Christoph Weiss

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L29/063 ,  H01L21/26506 ,  H01L21/28568 ,  H01L29/0607 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/36 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66136 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66674 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/861

Abstract: A semiconductor device includes a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing lifetime and/or mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.

Abstract translation: 半导体器件包括具有第一导电类型的第一电荷载流子的第一半导体区域和具有第二电荷载流子的第二半导体区域。 第一半导体区域包括与第二半导体区域接触的过渡区域，该过渡区域具有第一电荷载流子的第一浓度，具有第二浓度的第一电荷载流子的接触区域，其中第二浓度高于 第一浓度，以及接触区域和过渡区域之间的损伤区域。 损伤区域被配置为与接触区域和过渡区域的第一电荷载流子的寿命和/或迁移率相比，减小损伤区域的第一电荷载体的寿命和/或迁移率。

公开(公告)号：US20160111528A1

公开(公告)日：2016-04-21

申请号：US14887520

申请日：2015-10-20

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Christian Jaege ,  Franz Josef Niedernostheide ,  Roman Baburske ,  Andre Rainer Stegner ,  Antonio Vellei

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/167 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7395 ,  H01L29/0607 ,  H01L29/0696 ,  H01L29/0813 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66333

Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone structure forms first pn junctions with body zones of the transistor cells. An auxiliary structure between the drift zone structure and a second surface at a rear side of the semiconductor body includes a first portion that contains deep level dopants requiring at least 150 meV to ionize. A collector structure directly adjoins the auxiliary structure. An injection efficiency of minority carriers from the collector structure into the drift zone structure varies along a direction parallel to the first surface at least in the transistor cell area.

Abstract translation: 半导体器件包括在晶体管单元区域中沿半导体本体的前侧的第一表面形成的晶体管单元。 漂移区结构与晶体管单元的体区形成第一pn结。 漂移区结构与半导体本体后侧的第二表面之间的辅助结构包括第一部分，其包含需要至少150meV的深层掺杂物以进行电离。 集电器结构直接邻接辅助结构。 至少在晶体管单元区域中，从集电极结构到漂移区结构的少数载流子的注入效率沿平行于第一表面的方向变化。

公开(公告)号：US20160093706A1

公开(公告)日：2016-03-31

申请号：US14866157

申请日：2015-09-25

Applicant: Infineon Technologies AG

Inventor： Philip Christoph Brandt ,  Francisco Javier Santos Rodriguez ,  Andre Rainer Stegner

IPC: H01L29/423 ,  H01L29/739 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/4236 ,  H01L21/02244 ,  H01L21/3086 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.

Abstract translation: 一种形成具有栅极电极的晶体管的方法包括在半导体衬底上形成牺牲层，在牺牲层上形成图案化层，图形化图案化层以形成图案化结构，在图案化结构的侧壁上形成间隔物， 图案化结构，使用间隔物作为蚀刻掩模蚀刻通过牺牲层，并蚀刻到半导体衬底中，从而在半导体衬底中形成沟槽，并且在半导体衬底中的沟槽中填充导电材料以形成栅电极。

公开(公告)号：US08853774B2

公开(公告)日：2014-10-07

申请号：US13690328

申请日：2012-11-30

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Hans Peter Felsl ,  Yvonne Gawlina ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Georg Seibert ,  Andre Rainer Stegner ,  Wolfgang Wagner

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract translation: 半导体器件包括在第一沟槽中包括第一栅电极的第一晶体管单元。 半导体器件还包括在第二沟槽中包括第二栅电极的第二晶体管单元，其中第一和第二栅极电连接。 半导体器件还包括在第一和第二沟槽之间的第三沟槽，其中第三沟槽从半导体本体的第一侧比第一和第二沟槽更深地延伸到半导体本体中。 半导体器件还包括覆盖第三沟槽的底侧和第三沟槽壁的第三沟槽中的电介质。