公开(公告)号：US10205016B2

公开(公告)日：2019-02-12

申请号：US15484206

申请日：2017-04-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Detlef Weber ,  Karl-Heinz Gebhardt

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/40 ,  H01L29/10 ,  H01L27/06 ,  H01L27/092

Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.

公开(公告)号：US10002959B2

公开(公告)日：2018-06-19

申请号：US15429282

申请日：2017-02-10

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L23/528 ,  H01L29/66 ,  H01L23/34

CPC classification number: H01L29/7804 ,  H01L23/34 ,  H01L23/5283 ,  H01L27/0705 ,  H01L27/0727 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/42304 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7813 ,  H01L29/7826 ,  H01L29/7835 ,  H01L29/8613

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a source contact, the source contact including a first and second source contact portion, and a gate electrode in a gate trench in the first main surface adjacent to a body region. The body region and a drift zone are disposed along a first direction parallel to the first main surface between the source region and a drain region. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region, the first source contact portion further including a portion of the semiconductor substrate between the source conductive material and the second source contact portion. The semiconductor device further includes a temperature sensor in the semiconductor substrate.

公开(公告)号：US09893178B2

公开(公告)日：2018-02-13

申请号：US15187889

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Franz Hirler

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/808 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/8083

Abstract: A semiconductor device includes a transistor formed in a semiconductor substrate having a main surface. The transistor includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, a gate trench adjacent to a first sidewall of the channel region, a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal, and a channel separation trench adjacent to a second sidewall of the channel region. The second sidewall faces the first sidewall via the channel region. The channel separation trench is filled with an insulating separation trench filling consisting of an insulating material in direct contact with the channel region. The source region and the drain region are disposed along a first direction. The first direction is parallel to the main surface.

公开(公告)号：US20170301791A1

公开(公告)日：2017-10-19

申请号：US15484206

申请日：2017-04-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Detlef Weber ,  Karl-Heinz Gebhardt

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L21/26586 ,  H01L21/823418 ,  H01L27/0623 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7835

Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.

公开(公告)号：US09608070B2

公开(公告)日：2017-03-28

申请号：US15139758

申请日：2016-04-27

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/4175 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/156 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

公开(公告)号：US20160322464A1

公开(公告)日：2016-11-03

申请号：US15139758

申请日：2016-04-27

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/4175 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/156 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

Abstract translation: 半导体器件包括具有第一主表面的半导体衬底中的场效应晶体管。 场效应晶体管包括源区域，漏极区域，体区域和在体区域处的栅电极。 栅极被配置为控制在体区中形成的沟道的导电性，并且栅电极设置在栅极沟槽中。 主体区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 主体区域具有沿着第一方向延伸的脊的形状，主体区域与源区域和漏极区域相邻。 所述半导体器件还包括源极接触和主体接触，所述源极触点电连接到源极端子，所述主体触点电连接到所述源极触点和所述主体区域。

公开(公告)号：US20160308044A1

公开(公告)日：2016-10-20

申请号：US15095615

申请日：2016-04-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7825 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66787

Abstract: A semiconductor device comprises a transistor in a semiconductor body having a first main surface. The transistor comprises a source region of a first conductivity type, a drain region, a body region of a second conductivity type, different from the first conductivity type, and a gate electrode disposed in gate trenches extending in a first direction parallel to the first main surface. The source region, the body region and the drain region are arranged along the first direction. The body region comprises first ridges extending along the first direction, the first ridges being disposed between adjacent gate trenches in the semiconductor body. The body region further comprises a second ridge. A width of the second ridge is larger than a width of the first ridges, the widths being measured in a second direction perpendicular to the first direction.

Abstract translation: 半导体器件包括具有第一主表面的半导体本体中的晶体管。 晶体管包括不同于第一导电类型的第一导电类型的源极区域，漏极区域，第二导电类型的体区域，以及设置在沿与第一主体平行的第一方向延伸的栅极沟槽中的栅电极 表面。 源极区域，主体区域和漏极区域沿着第一方向布置。 主体区域包括沿着第一方向延伸的第一脊，第一脊设置在半导体本体中的相邻栅极沟槽之间。 身体区域还包括第二脊。 第二脊的宽度大于第一脊的宽度，宽度在垂直于第一方向的第二方向上被测量。

公开(公告)号：US20160307996A1

公开(公告)日：2016-10-20

申请号：US15081423

申请日：2016-03-25

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1008 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825

Abstract: A semiconductor device comprises a transistor in a semiconductor body having a first main surface and a second main surface, the first main surface being opposite to the second main surface. The transistor comprises a source region at the first main surface, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The gate electrode is disposed in trenches extending in the first direction. The transistor further comprises an insulating layer adjacent to the second main surface of the body region. The source region vertically extends to the second main surface.

Abstract translation: 半导体器件包括在具有第一主表面和第二主表面的半导体本体中的晶体管，第一主表面与第二主表面相对。 晶体管包括在第一主表面处的源极区域，漏极区域，体区域，漂移区域和在体区域处的栅电极。 主体区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 栅电极设置在沿第一方向延伸的沟槽中。 晶体管还包括与身体区域的第二主表面相邻的绝缘层。 源极区垂直延伸到第二主表面。

公开(公告)号：US09450085B2

公开(公告)日：2016-09-20

申请号：US14548375

申请日：2014-11-20

Applicant: Infineon Technologies AG

Inventor： Till Schloesser ,  Andreas Meiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734

Abstract: A semiconductor device includes a semiconductor substrate having first regions of a first conductivity type and body regions of the first conductivity type, which are arranged in a manner adjoining the first region and overlap the latter in each case on a side of the first region which faces a first surface of the semiconductor substrate, and having a multiplicity of drift zone regions arranged between the first regions and composed of a semiconductor material of a second conductivity type, which is different than the first conductivity type. The first regions and the drift zone regions are arranged alternately and form a superjunction structure. The semiconductor device further includes a gate electrode formed in a trench in the semiconductor substrate.

Abstract translation: 半导体器件包括具有第一导电类型的第一区域和第一导电类型的主体区域的半导体衬底，它们以与第一区域相邻的方式布置，并且在每种情况下与第一区域的第一区域重叠， 半导体衬底的第一表面，并且具有布置在第一区域之间并由与第一导电类型不同的第二导电类型的半导体材料构成的多个漂移区域。 第一区域和漂移区域交替布置并形成超结构结构。 半导体器件还包括形成在半导体衬底中的沟槽中的栅电极。

公开(公告)号：US09054181B2

公开(公告)日：2015-06-09

申请号：US13828894

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7818 ,  H01L29/7824 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode being adjacent to the body region. The body region, the drift zone, the source region and the drain region are disposed in a first semiconductor layer having a first main surface. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The transistor further includes a drift control region arranged adjacent to the drift zone, the drift control region being disposed over the first main surface.

Abstract translation: 半导体器件包括晶体管。 晶体管包括源区域，漏极区域，体区域，漂移区域和与身体区域相邻的栅电极。 体区，漂移区，源区和漏区设置在具有第一主表面的第一半导体层中。 主体区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 晶体管还包括与漂移区相邻布置的漂移控制区，漂移控制区设置在第一主表面上。