公开(公告)号：US20220059166A1

公开(公告)日：2022-02-24

申请号：US16947886

申请日：2020-08-21

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Mase J. Taub ,  DerChang Kau

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

Abstract: A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.

公开(公告)号：US10032508B1

公开(公告)日：2018-07-24

申请号：US15396224

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US20180190353A1

公开(公告)日：2018-07-05

申请号：US15396224

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Daniel Chu ,  Lark-Hoon Leem ,  John Gorman ,  Mase Taub ,  Sandeep Guliani ,  Kiran Pangal

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/12 ,  G11C2213/71

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

公开(公告)号：US20160372193A1

公开(公告)日：2016-12-22

申请号：US15180556

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： Arjun Kripanidhi ,  Kiran Pangal ,  Lark-Hoon Leem ,  Balaji Srinivasan

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0066

Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了在相变存储器中的读取和写入操作以减少突发干扰。 在一个实施例中，一种装置包括读取电路，用于将读取电压施加到相变存储器（PCM）单元，响应于读取电压的应用，将回退脉冲施加到PCM单元，其中挫折脉冲是 对于被配置为将PCM单元从非晶状态转换为结晶状态的规则设定脉冲，对于比第二时间段短的第一时间段执行的更短的设定脉冲，感测电路与应用同时感测 的挫折脉冲，PCM单元是处于非晶态还是结晶状态。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160284398A1

公开(公告)日：2016-09-29

申请号：US14671471

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Arjun Kripanidhi ,  Kiran Pangal ,  Lark-Hoon Leem ,  Balaji Srinivasan

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0066

Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

公开(公告)号：US20160093375A1

公开(公告)日：2016-03-31

申请号：US14850152

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，包括第一感测电路电容和第二感测电路电容，所述感测电路经配置以将所选择的GWL，LWL和第一感测电路电容预充电至WL偏置电压WLVDM，产生利用电荷的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。