公开(公告)号：US20220068833A1

公开(公告)日：2022-03-03

申请号：US17088618

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/495

Abstract: The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.

公开(公告)号：US20210385948A1

公开(公告)日：2021-12-09

申请号：US17411064

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Tin Poay CHUAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM

IPC: H05K1/11

Abstract: The present disclosure relates to a printed circuit board assembly including a first circuit board including a first footprint, the first circuit board further includes a plurality of first vertical vias extending between a first side and an opposing second side; a second circuit board including a second footprint smaller than the first footprint, the second circuit board further includes a plurality of second vertical vias extending between a subsequent first side and an opposing subsequent second side; an adhesive layer coupling the first side to the subsequent first side; and a plurality of third vertical vias extending through the first side and the subsequent first side.

公开(公告)号：US20210233875A1

公开(公告)日：2021-07-29

申请号：US17229316

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Tin Poay CHUAH ,  Chin Lee KUAN

IPC: H01L23/64 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H01L23/50

Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US20190279949A1

公开(公告)日：2019-09-12

申请号：US16462197

申请日：2017-11-20

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Tin Poay CHUAH ,  Chin Lee KUAN

IPC: H01L23/64 ,  H01L23/498 ,  H05K1/18

Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US20240145368A1

公开(公告)日：2024-05-02

申请号：US17975662

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Ravindra RUDRARAJU ,  Vijay KASTURI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14361

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a package substrate with a top substrate surface and an interposer coupled to the package substrate at the top substrate surface. The interposer may include a plurality of through interposer vias and an opening extending through the interposer. A power module may be arranged in the opening in the interposer and coupled to the package substrate at the top substrate surface. The power module may include a plurality of interconnects including a first interconnect coupled to a first voltage and a second interconnect coupled to a second voltage.

公开(公告)号：US20240006786A1

公开(公告)日：2024-01-04

申请号：US17857051

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Howe Yin LOO ,  Tin Poay CHUAH ,  Jenny Shio Yin ONG ,  Chee Min LOH ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Seok Ling LIM ,  Kooi Chi OOI

IPC: H01R12/57 ,  H01R12/70

CPC classification number: H01R12/57 ,  H01R12/7082 ,  H01R12/707

Abstract: The present disclosure is directed to a printed circuit board having a composite upper surface with a first section of a first-type of printed circuit board and a second section of a second-type of printed circuit board, for which the first section of the first-type of printed circuit board and the second section of the second-type of printed circuit board are coupled, respectively, to at least one device that is configured to abridge the first and second sections of the composite upper surface. In an aspect, the second-type of printed circuit board is configured to be embedded in the first-type of printed circuit board and the first-type of printed circuit board is configured to receive the second-type of printed circuit board.

公开(公告)号：US20240006324A1

公开(公告)日：2024-01-04

申请号：US17857057

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/5386 ,  H01L2924/1436 ,  H01L2924/1432 ,  H01L2924/1421 ,  H01L2924/3511 ,  H01L2924/30101 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: A semiconductor package includes a package substrate, a base die including a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface, and a first device including a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface. The semiconductor package further includes a second device including a third device surface coupled to the second device surface, and a fourth device surface opposite to the third device surface, and a bridge including a first portion coupled to the package substrate, and a second portion coupled to the first portion, the fourth device surface and the second die surface.

公开(公告)号：US20220068843A1

公开(公告)日：2022-03-03

申请号：US17090926

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48

Abstract: According to the various aspects, a package substrate with a heterogeneous substrate core including a first core layer that is coextensive with the package substrate and extends through a first section and a second section of the substrate core, in which the first section is adjacent to and thicker than the second section. The first section having at least a second layer and/or a third layer to provide the difference in thickness with the second section.

公开(公告)号：US20220068841A1

公开(公告)日：2022-03-03

申请号：US17088606

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Seok Ling LIM ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48

Abstract: According to various examples, a device is described. The device may include a stiffener member including a first step section and a second step section. The device may also include a plurality of vias extending from or through the stiffener member. The device may be coupled to a printed circuit board.

公开(公告)号：US20220068782A1

公开(公告)日：2022-03-03

申请号：US17089749

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jackson Chung Peng KONG ,  Jenny Shio Yin ONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/13

Abstract: According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.