公开(公告)号：US20210359110A1

公开(公告)日：2021-11-18

申请号：US17390483

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Michael L. HATTENDORF ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08

Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.

公开(公告)号：US20210143051A1

公开(公告)日：2021-05-13

申请号：US17151083

申请日：2021-01-15

Applicant: Intel Corporation

Inventor： Michael L. HATTENDORF ,  Curtis WARD ,  Heidi M. MEYER ,  Tahir GHANI ,  Christopher P. AUTH

IPC: H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

公开(公告)号：US20210091206A1

公开(公告)日：2021-03-25

申请号：US17100689

申请日：2020-11-20

Applicant: Intel Corporation

Inventor： Byron HO ,  Steven JALOVIAR ,  Jeffrey S. LEIB ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

公开(公告)号：US20200321333A1

公开(公告)日：2020-10-08

申请号：US16906680

申请日：2020-06-19

Applicant: Intel Corporation

Inventor： Byron HO ,  Chun-Kuo HUANG ,  Erica THOMPSON ,  Jeanne LUCE ,  Michael L. HATTENDORF ,  Christopher P. AUTH ,  Ebony L. MAYS

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

公开(公告)号：US20200058761A1

公开(公告)日：2020-02-20

申请号：US16342865

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Byron HO ,  Michael L. HATTENDORF ,  Jeanne L. LUCE ,  Ebony L. MAYS ,  Erica J. THOMPSON

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/762

Abstract: Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.

公开(公告)号：US20200027965A1

公开(公告)日：2020-01-23

申请号：US16509395

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Subhash M. JOSHI ,  Jeffrey S. LEIB ,  Michael L. HATTENDORF

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

公开(公告)号：US20190165146A1

公开(公告)日：2019-05-30

申请号：US16170600

申请日：2018-10-25

Applicant: Intel Corporation

Inventor： Byron HO ,  Steven JALOVIAR ,  Jeffrey S. LEIB ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

公开(公告)号：US20170323965A1

公开(公告)日：2017-11-09

申请号：US15654597

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Michael L. HATTENDORF ,  Pragyansri PATHI ,  Michael K. HARPER

IPC: H01L29/78 ,  H01L29/423 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.

公开(公告)号：US20250142939A1

公开(公告)日：2025-05-01

申请号：US19008393

申请日：2025-01-02

Applicant: Intel Corporation

Inventor： Jeffrey S. LEIB ,  Srijit MUKHERJEE ,  Vinay BHAGWAT ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H10D84/01 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B10/00 ,  H10D1/47 ,  H10D30/62 ,  H10D30/69 ,  H10D62/13 ,  H10D64/01 ,  H10D64/68 ,  H10D84/03 ,  H10D84/85

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

公开(公告)号：US20250126869A1

公开(公告)日：2025-04-17

申请号：US18999923

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Subhash JOSHI ,  Michael J. JACKSON ,  Michael L. HATTENDORF

IPC: H10D64/01 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B10/00 ,  H10D1/47 ,  H10D30/01 ,  H10D30/62 ,  H10D30/69 ,  H10D62/00 ,  H10D62/10 ,  H10D62/13 ,  H10D62/822 ,  H10D62/834 ,  H10D64/23 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83 ,  H10D84/85 ,  H10D89/10

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.