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    Elliptic curve hardware integrated circuit
    21.
    发明授权
    Elliptic curve hardware integrated circuit 有权

    公开(公告)号：US09967098B2

    公开(公告)日：2018-05-08

    申请号：US14757658

    申请日：2015-12-23

    申请人： Intel Corporation

    发明人： Santosh Ghosh ,  Manoj R Sastry

    IPC分类号： H04L29/00 ,  H04L9/30 ,  H04L9/14

    CPC分类号： H04L9/3066 ,  G06F7/725 ,  G09C1/00 ,  H04L9/14 ,  H04L2209/12 ,  H04L2209/24

    摘要： Embodiments of a system for, and method for using, an elliptic curve cryptography integrated circuit are generally described herein. An elliptic curve cryptography (ECC) operation request may be received. One of a plurality of circuit portions may be instructed to perform the ECC operation. The plurality of circuit portions that may be used include a finite field arithmetic circuit portion, an EC point addition and doubler circuit portion, a finite field exponentiation circuit portion, and a point multiplier circuit portion. The result of the ECC operation may then be output.

    ACCELERATING FOUR-WAY PARALLEL KECCAK EXECUTION ON 256-BIT VECTOR PROCESSOR
    27.
    发明公开
    ACCELERATING FOUR-WAY PARALLEL KECCAK EXECUTION ON 256-BIT VECTOR PROCESSOR 审中-公开

    公开(公告)号：US20240211261A1

    公开(公告)日：2024-06-27

    申请号：US18145776

    申请日：2022-12-22

    申请人： Intel Corporation

    发明人： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30029 ,  G06F9/30032

    摘要： A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rotated XOR result.

    PROCESSOR HARDWARE AND INSTRUCTIONS FOR VECTORIZED FUSED AND-XOR
    28.
    发明公开
    PROCESSOR HARDWARE AND INSTRUCTIONS FOR VECTORIZED FUSED AND-XOR 审中-公开

    公开(公告)号：US20230305846A1

    公开(公告)日：2023-09-28

    申请号：US17703194

    申请日：2022-03-24

    申请人： Intel Corporation

    发明人： Andrew H. Reinders ,  Santosh Ghosh ,  Manoj Sastry

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30145 ,  G06F9/30036 ,  G06F9/30029 ,  G06F9/3001 ,  G06F9/3802

    摘要： A method comprises fetching, by fetch circuitry, an encoded vectorized AND-XOR instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and a destination identifier, decoding, by decode circuitry, the decoded vectorized AND-XOR instruction to generate a decoded vectorized AND-XOR instruction, and executing, by execution circuitry, the decoded vectorized AND-XOR instruction to retrieve operands representing a product coefficient at an index position from the first source, a coefficient of a first polynomial from the second source, and a coefficient of a second polynomial from the third source, perform, in an atomic fashion, a vectorized AND-XOR operation to generate updated value of the product coefficient, and store the product coefficient of the output polynomial in a register file accessible to the execution circuitry.