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公开(公告)号：US10691617B2
公开(公告)日：2020-06-23
申请号：US16113174
申请日：2018-08-27
申请人： Intel Corporation
发明人： Abhishek R. Appu , Joydeep Ray , James A. Valerio , Altug Koker , Prasoonkumar P. Surti , Balaji Vembu , Wenyin Fu , Bhushan M. Borole , Kamal Sinha
IPC分类号： G06F12/12 , G06F12/128 , G06F12/0811 , G06F13/40 , G06T1/60 , G06F12/0897 , G06F12/084
摘要： A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
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公开(公告)号：US20190213161A1
公开(公告)日：2019-07-11
申请号：US16354312
申请日：2019-03-15
申请人： Intel Corporation
发明人： Anupama A. Thaploo , Bhushan M. Borole , Bee Ngo , Iqbal R. Rajwani , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
IPC分类号： G06F13/40 , G06F9/30 , G11C17/18 , G11C11/4094 , G11C17/16
CPC分类号： G06F13/4068 , G06F9/30105 , G06F9/30141 , G06F13/4077 , G11C7/12 , G11C11/4094 , G11C17/16 , G11C17/18
摘要： By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.
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公开(公告)号：US20180308450A1
公开(公告)日：2018-10-25
申请号：US15493606
申请日：2017-04-21
申请人： Intel Corporation
发明人： Abhishek R. Appu , Eric J. Hoekstra , Subramaniam Maiyuran , Prasoonkumar Surti , Eric G. Liskay , Joydeep Ray , Michael J. Norris , Wenyin Fu , Altug Koker
IPC分类号： G09G5/02
CPC分类号： G09G5/02 , G09G2340/06 , G09G2350/00
摘要： Methods and apparatus relating to techniques for provision of color mapping for better compression ratio are described. In an embodiment, a plurality of bits are moved from all channels of a first Red Green Blue Alpha (RGBA) space to an alpha channel of a second RGBA space. The plurality of the bits are selected from higher order bits of the first RGBA space. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180308208A1
公开(公告)日：2018-10-25
申请号：US15819093
申请日：2017-11-21
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
CPC分类号： G06T1/20 , G06F8/41 , G06F9/45533 , G06F9/5061 , G06F9/5094 , G06F17/16 , G06F2009/45583 , G06T1/60
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type
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公开(公告)号：US10102149B1
公开(公告)日：2018-10-16
申请号：US15488840
申请日：2017-04-17
申请人： Intel Corporation
发明人： Abhishek R. Appu , Joydeep Ray , James A. Valerio , Altug Koker , Prasoonkumar P. Surti , Balaji Vembu , Wenyin Fu , Bhushan M. Borole , Kamal Sinha
IPC分类号： G06F12/12 , G06F12/128 , G06F12/0811 , G06F13/40 , G06T1/20
摘要： A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
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公开(公告)号：US20180293702A1
公开(公告)日：2018-10-11
申请号：US15483059
申请日：2017-04-10
申请人： Intel Corporation
发明人： Abhishek R. Appu , Joydeep Ray , Altug Koker , Balaji Vembu , Prasoonkumar P. Surti , Kamal Sinha , Vasanth Ranganathan , Kiran C. Veernapu , Bhushan M. Borole , Wenyin Fu
CPC分类号： G06T1/60 , G06T1/20 , G06T15/005
摘要： In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
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27.发明授权公开(公告)号：US12007824B2
公开(公告)日：2024-06-11
申请号：US17517090
申请日：2021-11-02
申请人： Intel Corporation
发明人： Altug Koker , Abhishek R. Appu , Bhushan M. Borole , Wenyin Fu , Kamal Sinha , Joydeep Ray
IPC分类号： G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G09G5/36
CPC分类号： G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G09G5/363 , G09G5/366 , G09G2310/066 , G09G2310/08 , G09G2340/02 , G09G2360/06 , G09G2360/08 , G09G2370/022 , G09G2370/16
摘要： In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
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公开(公告)号：US11263720B2
公开(公告)日：2022-03-01
申请号：US16985329
申请日：2020-08-05
申请人： Intel Corporation
发明人： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
摘要： A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US11222392B2
公开(公告)日：2022-01-11
申请号：US16531763
申请日：2019-08-05
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
IPC分类号： G06T1/20 , G06T1/60 , G09G5/36 , G06F3/06 , G06N3/08 , G06F3/14 , G06N3/04 , G06N3/063 , G09G5/00
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.
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公开(公告)号：US20210294560A1
公开(公告)日：2021-09-23
申请号：US17162864
申请日：2021-01-29
申请人： Intel Corporation
发明人： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Altug Koker , Michael Apodaca , Kai Xiao , Jeffery S. Boles , Adam T. Lake , David M. Cimini , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Jacek Kwiatkowski , Philip R. Laws , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Wenyin Fu , Nikos Kaburlasos , Prasoonkumar Surti , Bhushan M. Borole
摘要： An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
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