公开(公告)号：US20120063241A1

公开(公告)日：2012-03-15

申请号：US13137745

申请日：2011-09-09

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C7/10

CPC分类号： G11C11/4097 ,  G11C2207/005

摘要： A semiconductor device has a hierarchical bit line structure and comprises first and second local bit lines transmitting first and second signals of first and second memory cells corresponding to a selected word line, and first and second global bit lines electrically connected to the first and second local bit lines through first and second switches, first and second sense amplifiers connected to the first and second global bit lines, and a control circuit. During a first period after the first and second memory cells are simultaneously accessed, the control circuit controls the first switch to conduction state so that the first sense amplifier amplifies the first signal and controls the second switch to non conduction state. During a second period after sensing of the first sense amplifier finishes, the control circuit controls the second switch to conduction state so that the second sense amplifier amplifies the second signal.

摘要翻译： 半导体器件具有分级位线结构，并且包括第一和第二本地位线，其传输与所选字线对应的第一和第二存储器单元的第一和第二信号，以及电连接到第一和第二本地的第一和第二全局位线 通过第一和第二开关的位线，连接到第一和第二全局位线的第一和第二读出放大器以及控制电路。 在同时访问第一和第二存储单元之后的第一时段期间，控制电路将第一开关控制到导通状态，使得第一读出放大器放大第一信号并将第二开关控制到非导通状态。 在感测到第一读出放大器结束之后的第二周期期间，控制电路将第二开关控制到导通状态，使得第二读出放大器放大第二信号。

公开(公告)号：US08068369B2

公开(公告)日：2011-11-29

申请号：US12461858

申请日：2009-08-26

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C16/06

CPC分类号： G11C7/067 ,  G11C11/4091 ,  G11C11/4097

摘要： A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.

摘要翻译： 单端读出放大器电路放大存储器单元的信号并通过位线传输，并且包括第一和第二MOS晶体管。 第一MOS晶体管向位线提供预定电压，并且响应于控制电压控制位线和感测节点之间的连接，并且第二MOS晶体管具有连接到感测节点的栅极，并且放大从 通过第一MOS晶体管的位线。 在读取操作之前将预定电压提供给位线，并将其设置为使得可以在电荷转移模式之间的变化点附近获得存储单元的高电平和低电平数据之间的感测节点处的所需电压差 以及在存储单元的读取电压范围内的电荷分配模式。

公开(公告)号：US20110248697A1

公开(公告)日：2011-10-13

申请号：US13064683

申请日：2011-04-08

申请人： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

发明人： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

IPC分类号： G05F3/08

CPC分类号： G11C5/147 ,  G11C7/04 ,  G11C11/4091

摘要： A semiconductor device comprises a first circuit outputting a signal to a first signal line, a first FET applied with a driving signal and having a gate electrode connected to a first node, a second FET controlling an electrical connection between the first signal line and the first node, a third FET amplifying a signal of the first node, a second circuit precharging the first signal line, and a voltage control circuit. A gate capacitance of the first FET is controlled in response to a voltage difference between the first node and the driving signal. The voltage control circuit shifts a potential of the driving signal when the second FET is non-conductive after the signal of the first-circuit is transmitted to the first node, and performs an offset control for the driving signal so as to compensate a variation of a threshold voltage of the first FET.

摘要翻译： 半导体器件包括将信号输出到第一信号线的第一电路，施加有驱动信号的第一FET并具有连接到第一节点的栅极;第二FET控制第一信号线与第一信号线之间的电连接 放大第一节点的信号的第三FET，对第一信号线预充电的第二电路和电压控制电路。 响应于第一节点和驱动信号之间的电压差来控制第一FET的栅极电容。 在第一电路的信号被发送到第一节点之后，当第二FET不导通时，电压控制电路移动驱动信号的电位，并且对驱动信号进行偏移控制，以补偿 第一FET的阈值电压。

公开(公告)号：US08017457B2

公开(公告)日：2011-09-13

申请号：US12149439

申请日：2008-05-01

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/101 ,  G11C11/005 ,  G11C13/00 ,  G11C13/0007 ,  G11C13/0033 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

摘要： A method of manufacturing a semiconductor memory device of the present invention consists of a step of forming a selection transistor and a separate selection transistor and a step of forming a variable resistance element and a capacitance element, characterized by forming the variable resistance element by sequentially laminating a first electrode that is connected to the selection transistor, a variable resistance layer, and a second electrode; forming the capacitance element by sequentially laminating a third electrode that is connected to the separate selection transistor, a dielectric layer, and a fourth electrode; forming the dielectric layer and the variable resistance layer with a mutually identical material; forming either one of the first electrode or the second electrode with the same material as the third electrode and the fourth electrode; and forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode.

摘要翻译： 本发明的半导体存储器件的制造方法由形成选择晶体管和单独的选择晶体管的步骤和形成可变电阻元件和电容元件的步骤构成，其特征在于，通过依次层叠形成可变电阻元件 连接到选择晶体管的第一电极，可变电阻层和第二电极; 通过依次层叠连接到分离的选择晶体管的第三电极，电介质层和第四电极来形成电容元件; 用相互相同的材料形成介电层和可变电阻层; 用与第三电极和第四电极相同的材料形成第一电极或第二电极中的任一个; 以及用与第三电极和第四电极不同的材料形成第一电极或第二电极中的另一个。

公开(公告)号：US20110205824A1

公开(公告)日：2011-08-25

申请号：US12929899

申请日：2011-02-23

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C11/4087 ,  G11C11/4096 ,  G11C2207/107

摘要： A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first semiconductor device in units of access units including a plurality of first definitions that define a plurality of burst lengths indicating numbers of different data, respectively, and a plurality of second definitions that define correspondences between certain elements of data among the plural data included in the blocks, respectively, and arrangement orders in the numbers of different data that constitute the burst lengths, respectively, and communicates with the first semiconductor device through the plural data in the numbers of different data according to the first and second definitions.

摘要翻译： 数据处理系统包括具有多个块的第一半导体器件，每个块包括多个数据;以及第二半导体器件，其具有控制第一半导体器件的第一控制电路，并且第一控制电路发出多个命令以与 所述第一半导体器件以接入单元为单位，包括分别定义指示不同数据的数目的多个突发长度的多个第一定义，以及多个第二定义，其定义包括在 各个块和分别构成突发长度的不同数据的数量的排列顺序，并且根据第一和第二定义通过多个不同数据的数据与第一半导体器件通信。

公开(公告)号：US07995373B2

公开(公告)日：2011-08-09

申请号：US12549124

申请日：2009-08-27

申请人： Kazuhiko Kajigaya ,  Eiichiro Kakehashi

发明人： Kazuhiko Kajigaya ,  Eiichiro Kakehashi

IPC分类号： G11C11/24

CPC分类号： G11C11/404 ,  G11C11/005 ,  G11C11/4076 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/32

摘要： A semiconductor memory device comprises a memory cell array and a forming controller. The memory cell array includes a plurality of first memory cells each having a structure in which dielectric material is sandwiched between two electrodes, and the memory cell array is divided into a plurality of areas capable of being designated. The forming controller controls to perform “forming” for the first memory cells in an area selectively designated from the plurality of areas of the memory cell array, and as a result of the forming, the first memory cells are changed to non-volatile second memory cells.

摘要翻译： 半导体存储器件包括存储单元阵列和成形控制器。 存储单元阵列包括多个第一存储单元，每个第一存储单元具有其中电介质材料夹在两个电极之间的结构，并且存储单元阵列被划分成能够被指定的多个区域。 成形控制器控制对从存储单元阵列的多个区域选择性地指定的区域中的第一存储单元执行“形成”，并且作为形成的结果，第一存储单元被改变为非易失性第二存储器 细胞。

公开(公告)号：US20110134678A1

公开(公告)日：2011-06-09

申请号：US12926693

申请日：2010-12-03

申请人： Takenori Sato ,  Kazuhiko Kajigaya ,  Yoshimitsu Yanagawa ,  Tomonori Sekiguchi ,  Akira Kotabe ,  Satoru Akiyama

发明人： Takenori Sato ,  Kazuhiko Kajigaya ,  Yoshimitsu Yanagawa ,  Tomonori Sekiguchi ,  Akira Kotabe ,  Satoru Akiyama

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/10876 ,  H01L27/10885

摘要： A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.

摘要翻译： 通过使用两个读出放大器进行时分执行相对于同时访问的两个存储单元的检测操作，然后同时执行恢复操作。 通过这种布置，不需要在全局位线的中间设置开关，并且在通过时分执行恢复操作时不会发生问题。 此外，由于第一读出放大器和第二读出放大器的寄生CR模型相互相同，因此可以保持高灵敏度。

公开(公告)号：US07773447B2

公开(公告)日：2010-08-10

申请号：US11976853

申请日：2007-10-29

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C8/00

CPC分类号： H03K19/177

摘要： A memory circuit of the invention comprises N look-up tables for implementing a desired logic function of L inputs/M outputs by partitioning a memory cell array including a plurality of memory cells into portions each corresponding to at least a predetermined number of input/output paths; a decode circuit for selecting one of the N look-up tables by decoding a look-up table select signal and for selecting M memory cells to be accessed included in the selected look-up table by decoding an L-bit logic input signal of the logic function; and a select connect circuit for selectively connecting the input/output paths of the M memory cells to be accessed with an input/output bus for transmitting an M-bit logic output signal of the logic function in response to a decoded result of the decode circuit.

摘要翻译： 本发明的存储器电路包括N个查找表，用于通过将包括多个存储器单元的存储单元阵列分成各自对应于至少预定数量的输入/输出的部分来实现L个输入/ M输出的所需逻辑功能 路径 解码电路，用于通过解码查找表选择信号并通过解码所选择的查找表中包括的M个要存储的M个存储单元来选择N个查找表中的一个， 逻辑功能; 以及选择连接电路，用于响应于解码电路的解码结果选择性地将要访问的M个存储器单元的输入/输出路径与用于发送逻辑功能的M位逻辑输出信号的输入/输出总线连接 。

公开(公告)号：US20100054018A1

公开(公告)日：2010-03-04

申请号：US12549124

申请日：2009-08-27

申请人： Kazuhiko Kajigaya ,  Eiichiro Kakehashii

发明人： Kazuhiko Kajigaya ,  Eiichiro Kakehashii

IPC分类号： G11C11/00 ,  G11C11/24 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C11/404 ,  G11C11/005 ,  G11C11/4076 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/32

摘要： A semiconductor memory device comprises a memory cell array and a forming controller. The memory cell array includes a plurality of first memory cells each having a structure in which dielectric material is sandwiched between two electrodes, and the memory cell array is divided into a plurality of areas capable of being designated. The forming controller controls to perform “forming” for the first memory cells in an area selectively designated from the plurality of areas of the memory cell array, and as a result of the forming, the first memory cells are changed to non-volatile second memory cells.

摘要翻译： 半导体存储器件包括存储单元阵列和成形控制器。 存储单元阵列包括多个第一存储单元，每个第一存储单元具有其中电介质材料夹在两个电极之间的结构，并且存储单元阵列被划分成能够被指定的多个区域。 成形控制器控制对从存储单元阵列的多个区域选择性地指定的区域中的第一存储单元执行“形成”，并且作为形成的结果，第一存储单元被改变为非易失性第二存储器 细胞。

公开(公告)号：US07663936B2

公开(公告)日：2010-02-16

申请号：US11907208

申请日：2007-10-10

申请人： Kazuhiko Kajigaya

发明人： Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C7/106 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/18 ,  G11C11/4093 ,  G11C11/4097

摘要： A semiconductor circuit of the invention comprises: a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers each for amplifying data of the memory cell connected to a selected word line through the bit line; a plurality of data holding circuits each for holding data transferred from the plurality of sense amplifiers; and a plurality of selectors each for selecting a data holding circuit from a unit group including a predetermined number of the data holding circuits based on logic input data, and for externally connecting one end of the selected data holding circuit.

摘要翻译： 本发明的半导体电路包括：存储单元阵列，包括形成在多个字线和多个位线之间的交叉处的多个存储单元; 多个读出放大器，每个用于放大通过位线连接到所选字线的存储单元的数据; 多个数据保持电路，用于保持从多个读出放大器传送的数据; 以及多个选择器，每个选择器用于从包括基于逻辑输入数据的预定数量的数据保持电路的单元组中选择数据保持电路，以及用于外部连接所选数据保持电路的一端。