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268 条记录 (耗时 0.024 秒)

    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
    21.
    发明授权
    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
    具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺

    公开(公告)号：US06348374B1

    公开(公告)日：2002-02-19

    申请号：US09597887

    申请日：2000-06-19

    申请人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    发明人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L218242

    CPC分类号： H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10885

    摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.

    摘要翻译： 一种形成垂直晶体管的方法。 在半导体衬底上形成衬垫层。 通过焊盘层和半导体衬底形成槽。 埋在槽中的位线形成。 位线被电介质材料包围。 形成延伸穿过介电材料的带，以将位线连接到半导体衬底。 槽被填充在位线上方的导体。 导体沿其纵向轴线切割，使得导体保持在槽的一侧。 在半导体衬底之上形成基本上与位线正交的字线槽。 导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。 字线形成在连接到单独的栅极导体的字线槽中。

    Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell
    23.
    发明授权
    Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell 失效
    制造在单元中具有多个并联连接的沟槽电容器的多端口存储器的方法

    公开(公告)号：US07485525B2

    公开(公告)日：2009-02-03

    申请号：US11306749

    申请日：2006-01-10

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

    IPC分类号： H01L21/8242

    CPC分类号： G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

    摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

    摘要翻译： 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。 这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。 第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。 在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

    6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI
    25.
    发明授权
    6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI 失效
    6F2沟槽EDRAM单元，具有双门控垂直MOSFET和自对准STI

    公开(公告)号：US06570208B2

    公开(公告)日：2003-05-27

    申请号：US09766013

    申请日：2001-01-18

    申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Gary B. Bronner

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L21/823481 ,  H01L21/823487

    摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

    摘要翻译： 提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与电池的字线和位线自对准的区域）的存储单元。 本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。 还提供了制造本发明的存储单元的方法。

    Static self-refreshing DRAM structure and operating mode
    26.
    发明授权
    Static self-refreshing DRAM structure and operating mode 失效
    静态自刷新DRAM结构和工作模式

    公开(公告)号：US06501117B1

    公开(公告)日：2002-12-31

    申请号：US10007846

    申请日：2001-11-05

    申请人： Carl J. Radens ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Jack A. Mandelman

    发明人： Carl J. Radens ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Jack A. Mandelman

    IPC分类号： H01L27108

    CPC分类号： H01L27/11 ,  G11C11/404 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L29/945

    摘要： A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT. A peripheral gate oxide layer, which coats sidewalls of the DT above the TTO, defines a space which is filled with the FET gate electrode. An outdiffusion region, doped with the first dopant type, is formed in the well region near the buried-strap. The cell has a first state and an opposite state of operation. A punch-through device, formed in the well between the outdiffusion region and the interface, provides a self-refreshing punchthrough current in the cell between the well and the plate in the first state of cell operation. A reverse bias junction leakage current occurs in the cell between the buried-strap and the P-well to refresh the opposite state of cell operation.

    摘要翻译： 在FET晶体管下方的深沟槽（DT）的底部形成DRAM单元存储电容器。 DT具有具有侧壁的上部，中部和下部。 围绕掺杂有第一掺杂剂类型的下部DT部分的电容器平板电极通过界面与围绕掺杂有相反掺杂剂类型的DT的上部和中部的阱区隔开。 形成在电池顶部的源极/漏极区掺杂有第一掺杂剂类型。 覆盖DT的下部和中心部分的侧壁和底部的节点电介质层填充有掺杂有第一掺杂剂类型的电容器的节点电极，填充第一掺杂剂类型的下部的节点电介质层内部的空间 DT。 在凹陷节点电介质层上方，带区域空间填充有埋地导体。 在DT上的节点电极和掩埋带上形成氧化物（TTO）层。 在TTO上方覆盖DT的侧壁的外围栅极氧化物层限定了用FET栅电极填充的空间。 在掩埋带附近的阱区中形成掺杂有第一掺杂剂类型的扩散区。 电池具有第一状态和相反的操作状态。 形成在扩散区域和界面之间的井中的穿通装置在电池操作的第一状态下在孔和板之间的电池单元中提供自刷新穿透电流。 在埋层和P阱之间的电池中产生反向偏置结漏电流，以刷新电池操作的相反状态。

    Structures and methods of anti-fuse formation in SOI
    28.
    发明授权
    Structures and methods of anti-fuse formation in SOI 失效
    SOI中抗熔丝形成的结构和方法

    公开(公告)号：US06972220B2

    公开(公告)日：2005-12-06

    申请号：US10366298

    申请日：2003-02-12

    申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12 ,  H01L21/00

    CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

    摘要翻译： 可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的反熔丝结构形成在复合衬底上，例如绝缘体上硅 通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。 反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。 绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。 由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。 因此实现了自动修复而不中断操作的可能性。