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21.发明申请公开(公告)号：US20090254788A1
公开(公告)日：2009-10-08
申请号：US12061752
申请日：2008-04-03
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/3187 , G11C29/12015 , G11C29/16 , G11C29/44 , G11C2029/0405 , G11C2029/3202
摘要： A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., “signature” of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.
摘要翻译： 一种用于执行IC器件实时LBIST诊断的方法，系统和计算机程序产品。 在LBIST期间，残留数据和测试周期的标识符保存在IC器件中（DUT）中。 如果压缩树桩数据与预定义的编码值（即测试周期的“签名”）不匹配，则保存的桩号数据和故障测试周期的标识符被保留，否则确定DUT通过测试 周期。 故障测试周期的标识符和残差用于分析错误，包括几乎不可重现的错误。
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22.发明申请System and Method of Integrated Circuit Control for in Situ Impedance Measurement 审中-公开用于现场阻抗测量的集成电路控制系统和方法公开(公告)号：US20080224714A1
公开(公告)日：2008-09-18
申请号：US11685226
申请日：2007-03-13
IPC分类号： G01R27/02
CPC分类号： G01R31/31922 , G01R27/02 , G01R31/31937
摘要： A system and method of integrated circuit control for in situ impedance measurement including a system with a plurality of functional partitions in a clocked logic type integrated circuit, the functional partitions having a communication controller and a modulation gate, the modulation gate receiving a clock signal and a modulation signal and generating a modulated clock signal for the functional partition; at least one of the communication controllers receiving an in-band signal and selectively communicating the in-band signal to the other communication controllers; and at least one of the functional partitions having a modulator, the modulator receiving the clock signal and a modulation control signal and generating the modulation signal.
摘要翻译： 一种用于原位阻抗测量的集成电路控制的系统和方法，包括在时钟逻辑型集成电路中具有多个功能分区的系统，功能分区具有通信控制器和调制门，调制门接收时钟信号， 调制信号并产生用于功能分区的调制时钟信号; 所述通信控制器中的至少一个接收带内信号并选择性地将所述带内信号传送到所述其他通信控制器; 并且功能分区中的至少一个具有调制器，调制器接收时钟信号和调制控制信号并产生调制信号。
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23.发明申请DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE 审中-公开用于测量和维护平衡时间周期的占空比测量电路公开(公告)号：US20080198700A1
公开(公告)日：2008-08-21
申请号：US12045059
申请日：2008-03-10
IPC分类号： G04F10/00
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译： 用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。 本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。 第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。 延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。 可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。
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公开(公告)号：US07313747B2
公开(公告)日：2007-12-25
申请号：US11388002
申请日：2006-03-23
IPC分类号： G01R31/30
CPC分类号： G01R31/318378
摘要： A computer implemented method, testing system, computer usable program code, and apparatus are provided for measuring microprocessor susceptibility to internal noise A noise generator modulates a clock signal to generate noise on a targeted component within a microprocessor. A function generator executes microprocessor functions on a plurality of functional components within the microprocessor. A maximum execution frequency on the plurality of functional components is then measured and a set of frequency ranges where the functional components are susceptible to the generated noise is determined.
摘要翻译： 提供了计算机实现的方法，测试系统，计算机可用程序代码和装置，用于测量微处理器对内部噪声的敏感性。噪声发生器调制时钟信号以在微处理器内的目标组件上产生噪声。 函数发生器在微处理器内的多个功能部件上执行微处理器功能。 然后测量多个功能组件上的最大执行频率，并且确定功能组件易于产生噪声的一组频率范围。
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25.发明授权Creating scan chain definition from high-level model using high-level model simulation 有权使用高级模型模拟从高级模型创建扫描链定义公开(公告)号：US08281279B2
公开(公告)日：2012-10-02
申请号：US12963246
申请日：2010-12-08
CPC分类号： G01R31/318583 , G06F17/505 , G06F2217/14
摘要： Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into chunks. For each chunk, the mechanisms identify the latches within the chunk that change at each shift. The mechanisms isolate the scan path latch when divergence occurs.
摘要翻译： 提供了使用高级模型模拟从高级模型创建移位寄存器定义的机制。 机制初始化所有潜在的扫描链锁存器，识别给定扫描链中的锁存器，并将扫描链锁存器分成多个块。 对于每个块，这些机制识别块中每个位移处的锁存器。 当出现发散时，机制将隔离扫描路径锁存器。
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26.发明授权System and method to reduce LBIST manufacturing test time of integrated circuits 失效减少LBIST制造测试时间集成电路的系统和方法公开(公告)号：US07519889B1
公开(公告)日：2009-04-14
申请号：US12060339
申请日：2008-04-01
IPC分类号： G01R31/28
CPC分类号： G01R31/318385
摘要： A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.
摘要翻译： 一种减少集成电路的自检制造测试时间内置逻辑的方法，其特征在于包括：将大量测试种子加载到本地可访问的本地设置在集成电路上的片上存储器阵列中， 与一组LBIST控制信息相关联; 在LBIST控制信息的集合控制下的LBIST操作期间，一次一个地将多个测试种子从本地可访问的片上存储器阵列发送到伪随机模式生成器中; 通过使用多个测试种子将随机比特流串行地生成到集成电路的多个并行移位寄存器中; 以及对所述集成电路中的多个逻辑块执行逻辑内置自检以检测所述集成电路内的缺陷。
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27.发明申请METHOD FOR BUILT IN SELF TEST FOR MEASURING TOTAL TIMING UNCERTAINTY IN A DIGITAL DATA PATH 审中-公开用于在数字数据路径中测量总时间不确定度的自检中的方法公开(公告)号：US20080198699A1
公开(公告)日：2008-08-21
申请号：US12045053
申请日：2008-03-10
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译： 用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。 本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。 第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。 延迟线抽头（逆变器输出）被输入到在进展由互补时钟对时钟控制通过延迟线来捕获发射时钟的进展和确定任何变型的寄存器（例如，从抖动，VDD噪声）。 可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。
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28.发明授权Built in self test circuit for measuring total timing uncertainty in a digital data path 有权内置自检电路，用于测量数字数据路径中的总时序不确定度公开(公告)号：US07400555B2
公开(公告)日：2008-07-15
申请号：US10712925
申请日：2003-11-13
CPC分类号： G01R31/31725 , G01R31/318594
摘要： A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
摘要翻译： 用于测量时钟数字路径中的定时不确定度的电路，特别是在任何时钟周期内完成的逻辑级数。 本地时钟缓冲器接收全局时钟并提供互补的本地时钟对。 第一本地（发射）时钟是延迟线的输入，例如，3个时钟周期的串联逆变器。 延迟线抽头（逆变器输出）是由互补时钟对计时的寄存器的输入，以通过延迟线捕获启动时钟的进程，并识别出该进程中的任何变化（例如抖动，VDD噪声）。 可以通过来自一对这样的时钟缓冲器的交叉耦合启动时钟来测量全局时钟偏移和跨芯片栅极长度变化，并且选择性地将本地和远程启动时钟传递到相应的延迟线。
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29.发明授权Test method for guaranteeing full stuck-at-fault coverage of a memory array 失效用于确保存储器阵列的完全卡在故障覆盖的测试方法公开(公告)号：US07073106B2
公开(公告)日：2006-07-04
申请号：US10392665
申请日：2003-03-19
IPC分类号： G11C29/00
CPC分类号： G11C29/024 , G11C15/00 , G11C29/02
摘要： A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.
摘要翻译： 一种用于测试故障故障的方法，计算机程序产品和系统。 第一寄存器可以加载第一值，其中第一值可以被写入存储器阵列中的每个条目。 第二个寄存器可以加载第二个值。 第三个寄存器可以加载第二个值或第三个值。 预先选择第二和第三值以使用模式测试选择器电路，其中模式包括要输入到选择器电路的一组位和要存储在存储器单元中的一组位。 存储在第二和第三寄存器中的最高有效位中的值可以被预解码以产生预代码值。 可以将预解码值与存储在阵列中的条目中的n个最高有效位中的值进行比较，以确定是否存在故障。
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公开(公告)号：US06665828B1
公开(公告)日：2003-12-16
申请号：US09664848
申请日：2000-09-19
IPC分类号： G01R3128
CPC分类号： G01R31/318555 , G01R31/318385 , G01R31/318536
摘要： A method and system for testing an integrated circuit (IC) comprising a plurality of logic units and a plurality of level sensitive scan design latches (LSSD) chains (scan chains) where the partitioning of the scan chains is different than the partitioning of the logic units. Scan blocks, each scan block comprising multiplexers, a pseudo random pattern generator (PRPG), a partitioned multiple input shift register (MISR), functional logic and control function logic are distributively placed around and close to scan inputs and scan outputs of the IC in otherwise unused area too small for larger functional logic blocks. The MISR, which contains many loaded latches and other logic, would normally be the largest element of the scan block has been partitioned into a sub-set of a full MISR to minimize the size of an individual scan block. The scan block has the functionality to enable LSSD testing, system testing and logic built in self test (LBIST) by the way the individual scan blocks are wired to the scan inputs and scan outputs of the logic units within the IC. Two or more scan blocks are needed to make a complete MISR depending on the sub-set partitioning of the MISR in each scan block. Scan block may have particular IC scan inputs and scan outputs wired into many different multiplexer inputs maintaining a known testability so wiring at the local level may be optimized. Since most of the wiring to the logic unit scan chains, wiring to the central scan switch is minimized reducing wiring complexity and cost. By partitioning the MISR, the size of the standardized Scan blocks is minimized allowing the most effective placement around logic units.
摘要翻译： 一种用于测试集成电路（IC）的方法和系统，该集成电路（IC）包括多个逻辑单元和多个电平敏感扫描设计锁存器（LSSD）链（扫描链），其中扫描链的划分不同于逻辑的分割 单位。 扫描块，包括多路复用器的每个扫描块，伪随机模式发生器（PRPG），分区多输入移位寄存器（MISR），功能逻辑和控制功能逻辑分布放置在IC的扫描输入和扫描输出周围并靠近 否则对于较大的功能逻辑块，未使用的区域太小。 包含许多加载锁存器和其他逻辑的MISR通常将被扫描块的最大元素划分成完整MISR的子集，以最小化单个扫描块的大小。 扫描块具有通过各个扫描块连接到IC内的逻辑单元的扫描输入和扫描输出的方式来启用LSSD测试，内部自检（LBIST）中的LSSD测试和逻辑功能。 需要两个或更多个扫描块来根据每个扫描块中的MISR的子集划分来完成MISR。 扫描块可能具有特定的IC扫描输入和连接到许多不同的多路复用器输入中的扫描输出，保持已知的可测试性，从而可以优化在局部级别的布线。 由于大多数逻辑单元的接线扫描链，所以将中央扫描开关的接线最小化，从而降低了布线的复杂性和成本。 通过划分MISR，可以将标准化的扫描块的大小最小化，从而最有效地放置在逻辑单元周围。
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