公开(公告)号：US20120184077A1

公开(公告)日：2012-07-19

申请号：US13100192

申请日：2011-05-03

申请人： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

发明人： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

IPC分类号： H01L21/336

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66659

摘要： An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

摘要翻译： 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括主要部分（240M或242M）和与主要部分横向连续并在栅电极下方横向延伸的更轻掺杂的横向延伸部（240E或242E）。 沿着上半导体表面终止沟道区的横向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源极的横向延伸比起漏极的横向延伸稍微掺杂，并且由原子量较高的掺杂剂限定。

公开(公告)号：US07973372B2

公开(公告)日：2011-07-05

申请号：US12382972

申请日：2009-03-27

申请人： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

发明人： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66659

摘要： An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is defined with dopant of higher atomic weight than the lateral extension of the drain.

摘要翻译： 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止通道区域的侧向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源的横向延伸由比排水管的横向延伸更高的原子量的掺杂剂限定。

公开(公告)号：US07247885B2

公开(公告)日：2007-07-24

申请号：US11137939

申请日：2005-05-26

申请人： Glenn H. Rankin ,  Sandeep R. Bahl

发明人： Glenn H. Rankin ,  Sandeep R. Bahl

IPC分类号： H01L27/15

CPC分类号： H01L33/025 ,  H01L33/0008 ,  H01L33/0054 ,  H01L33/34

摘要： In one aspect, a first region that includes a first Group IV semiconductor that has a bandgap and is doped with a first dopant of a first electrical conductivity type is formed. A pattern is created. The pattern controls formation of local crystal modifications in the first Group IV semiconductor in an array. An array of local crystal modifications is formed in the first Group IV semiconductor in accordance with the pattern. The local crystal modifications induce overlapping strain fields that increase the bandgap of the first Group IV semiconductor, create an energy band barrier against transport of minority carriers across the first region. A second region that includes a second Group IV semiconductor that has a bandgap and is doped with a second dopant of a second electrical conductivity type opposite the first conductivity type is formed. Semiconductor devices formed in accordance with this method also are described.

摘要翻译： 一方面，形成包括具有带隙并掺杂有第一导电类型的第一掺杂物的第一IV族半导体的第一区域。 创建模式。 该图案控制阵列中第一组IV半导体中局部晶体修饰的形成。 根据图案，在第一组IV半导体中形成局部晶体修改阵列。 局部晶体修饰引起叠加的应变场，其增加第一组IV半导体的带隙，从而产生抵抗少数载流子跨越第一区域传输的能带屏障。 形成第二区域，其包括具有带隙并掺杂有与第一导电类型相反的第二导电类型的第二掺杂剂的第二IV族半导体。 还描述了根据该方法形成的半导体器件。

公开(公告)号：US08946780B2

公开(公告)日：2015-02-03

申请号：US13037974

申请日：2011-03-01

申请人： Sandeep R. Bahl ,  Richard W. Foote, Jr.

发明人： Sandeep R. Bahl ,  Richard W. Foote, Jr.

IPC分类号： H01L21/285 ,  H01L21/02 ,  H01L29/45 ,  H01L29/778 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/66462

摘要： A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.

摘要翻译： 半导体器件包括在第一层上的第一层和第二层。 第一层和第二层被配置为在第一层和第二层的界面处形成电子气层。 半导体器件还包括通过第二层的欧姆接触和多个导电通孔。 导电通孔被配置为将欧姆接触电耦合到电子气体层。 导电通孔可以具有基本上垂直的侧壁或基本上倾斜的侧壁，或者导电通孔可以在欧姆接触件上形成纳米纹理表面。 第一层可以包括III族氮化物成核，缓冲层和沟道层，第二层可以包括III族氮化物阻挡层。

公开(公告)号：US07307327B2

公开(公告)日：2007-12-11

申请号：US11197004

申请日：2005-08-04

申请人： Sandeep R. Bahl ,  Frederick P. LaMaster ,  David W. Bigelow

发明人： Sandeep R. Bahl ,  Frederick P. LaMaster ,  David W. Bigelow

IPC分类号： H01L31/00

CPC分类号： H01L27/14687 ,  H01L27/1463 ,  H01L27/14649

摘要： CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.

摘要翻译： 具有高灵敏度和低串扰的CMOS图像传感器，特别是在远红外到红外波长的CMOS图像传感器以及CMOS图像传感器的制造方法。 CMOS图像传感器具有衬底，衬底上方的外延层以及延伸到用于接收光的外延层中的多个像素。 图像传感器还包括在衬底和外延层之间的水平阻挡层中的至少一个，用于防止在衬底中产生的载流子移动到外延层，以及在多个像素中的相邻像素之间的多个横向势垒层， 防止电子在外延层中的横向扩散。

公开(公告)号：US08318563B2

公开(公告)日：2012-11-27

申请号：US12800606

申请日：2010-05-19

申请人： Sandeep R. Bahl ,  Abdalla Naem

发明人： Sandeep R. Bahl ,  Abdalla Naem

IPC分类号： H01L21/336

CPC分类号： H01L21/8258 ,  H01L29/2003 ,  H01L29/7785

摘要： A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools.

摘要翻译： 一种方法包括在半导体衬底上形成非连续外延层。 衬底包括由沟槽分离的多个台面。 该外延层包括至少在衬底的台面上的晶体III族氮化物部分。 该方法还包括在沟槽中沉积电介质材料。 该方法还可以包括在台面和沟槽的侧壁上形成间隔物，或在衬底上形成在台面顶部开口的掩模。 外延层还可以在沟槽底部包括III族氮化物部分。 该方法还可以包括在至少一个晶体III族氮化物部分上形成栅极结构，源极和漏极接触，导电互连和导电插塞，其中至少一些互连和插塞至少部分地在沟槽上方。 栅极结构，源极和漏极接触，互连和插塞可以使用标准硅加工工具形成。

公开(公告)号：US07608471B2

公开(公告)日：2009-10-27

申请号：US11199663

申请日：2005-08-09

申请人： Sandeep R. Bahl

发明人： Sandeep R. Bahl

IPC分类号： H01L21/00

CPC分类号： H01L21/2007 ,  H01L21/6835 ,  H01L21/8258 ,  H01L23/544 ,  H01L2221/68363 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method and apparatus for fabricating semiconductor devices, for example, III-V semiconductor devices, having a desired substrate, for example, a silicon substrate. A method for fabricating semiconductor devices includes providing a semiconductor wafer that includes a plurality of semiconductor structures attached to a native substrate formed of a first substrate material, and a host substrate formed of a second substrate material. At least one subset of semiconductor structures of the plurality of semiconductor structures is transferred from the semiconductor wafer to the host substrate to provide a semiconductor device having a substrate formed of the second substrate material.

摘要翻译： 用于制造半导体器件的方法和装置，例如具有所需衬底例如硅衬底的III-V半导体器件。 一种制造半导体器件的方法包括提供半导体晶片，其包括附接到由第一基板材料形成的天然基板的多个半导体结构以及由第二基板材料形成的主体基板。 多个半导体结构的半导体结构的至少一个子集从半导体晶片转移到主基板，以提供具有由第二基板材料形成的基板的半导体器件。

公开(公告)号：US07592654B2

公开(公告)日：2009-09-22

申请号：US11940569

申请日：2007-11-15

申请人： Sandeep R. Bahl ,  Fredrick P. LaMaster ,  David W. Bigelow

发明人： Sandeep R. Bahl ,  Fredrick P. LaMaster ,  David W. Bigelow

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L27/14 ,  H01L31/00 ,  H01L31/0232 ,  H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00 ,  H01L29/417 ,  H01L29/732 ,  H01L27/148

CPC分类号： H01L27/14687 ,  H01L27/1463 ,  H01L27/14649

摘要： CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.

摘要翻译： 具有高灵敏度和低串扰的CMOS图像传感器，特别是在远红外到红外波长的CMOS图像传感器以及CMOS图像传感器的制造方法。 CMOS图像传感器具有衬底，衬底上方的外延层以及延伸到用于接收光的外延层的多个像素。 图像传感器还包括在衬底和外延层之间的水平阻挡层中的至少一个，用于防止在衬底中产生的载流子移动到外延层，以及在多个像素中的相邻像素之间的多个横向势垒层， 防止电子在外延层中的横向扩散。

公开(公告)号：US08592292B2

公开(公告)日：2013-11-26

申请号：US12807336

申请日：2010-09-02

申请人： Sandeep R. Bahl ,  Jamal Ramdani

发明人： Sandeep R. Bahl ,  Jamal Ramdani

IPC分类号： H01L21/20

CPC分类号： H01L21/762 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/7605 ,  H01L23/485 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

公开(公告)号：US20110284859A1

公开(公告)日：2011-11-24

申请号：US12800606

申请日：2010-05-19

申请人： Sandeep R. Bahl ,  Abdalla Naem

发明人： Sandeep R. Bahl ,  Abdalla Naem

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L21/8258 ,  H01L29/2003 ,  H01L29/7785

摘要： A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools.

摘要翻译： 一种方法包括在半导体衬底上形成非连续外延层。 衬底包括由沟槽分离的多个台面。 该外延层包括至少在衬底的台面上的晶体III族氮化物部分。 该方法还包括在沟槽中沉积电介质材料。 该方法还可以包括在台面和沟槽的侧壁上形成间隔物，或在衬底上形成在台面顶部开口的掩模。 外延层还可以在沟槽底部包括III族氮化物部分。 该方法还可以包括在至少一个晶体III族氮化物部分上形成栅极结构，源极和漏极接触，导电互连和导电插塞，其中至少一些互连和插塞至少部分地在沟槽上方。 栅极结构，源极和漏极接触，互连和插塞可以使用标准硅加工工具形成。