公开(公告)号：US20090268510A1

公开(公告)日：2009-10-29

申请号：US12108548

申请日：2008-04-24

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Hoki Kim ,  Geng Wang

IPC分类号： G11C11/24 ,  H01L21/8242

CPC分类号： H01L27/10829 ,  G11C7/02 ,  G11C11/4099 ,  H01L27/10861 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.

摘要翻译： 公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。 该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。 两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。 此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。 还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

公开(公告)号：US20090193186A1

公开(公告)日：2009-07-30

申请号：US12019818

申请日：2008-01-25

申请人： John E. Barth, JR. ,  Philip G. Emma ,  Hillery C. Hunter ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth, JR. ,  Philip G. Emma ,  Hillery C. Hunter ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0862 ,  Y02D10/13

摘要： An embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful.

摘要翻译： 描述了具有多次使用刷新周期的嵌入式DRAM（eDRAM）。 在一个实施例中，存在多级高速缓冲存储器系统，其包括被配置为从高速缓存的至少一个级别接收未决的预取操作的等待写入队列。 预取队列被配置为接收至少一个缓存级别的预取操作。 刷新控制器被配置为确定要刷新到期的每个高速缓存级别内的地址。 刷新控制器被配置为断言刷新写入信号以写入从针对刷新而不是刷新现有数据的地址指定的等待写入队列提供的数据。 刷新控制器响应于确定有未决数据提供给被指定为刷新的地址，来确定刷新写入信号。 刷新控制器还被配置为响应于确定刷新的数据是有用的，将更新读出信号断言以将更新的数据发送到较高级别的高速缓存的预取队列作为预取操作。

公开(公告)号：US20120205732A1

公开(公告)日：2012-08-16

申请号：US13454635

申请日：2012-04-24

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.

摘要翻译： 集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器 有源晶体管。

公开(公告)号：US20120083091A1

公开(公告)日：2012-04-05

申请号：US13324486

申请日：2011-12-13

申请人： John E. Barth, JR. ,  Kerry Bernstein

发明人： John E. Barth, JR. ,  Kerry Bernstein

IPC分类号： H01L21/02

CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L23/535 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.

摘要翻译： 半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区和第一极性类型的扩散区的掩埋绝缘体层的顶部上的有源半导体层， 第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽 设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

公开(公告)号：US20110051532A1

公开(公告)日：2011-03-03

申请号：US12550848

申请日：2009-08-31

申请人： John E. Barth, JR. ,  Erik A. Nelson

发明人： John E. Barth, JR. ,  Erik A. Nelson

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C7/065 ,  G11C7/12

摘要： An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset that compensates for device mismatch and voltage threshold of a sense amplifier.

摘要翻译： 描述了一种为感测放大器提供具有偏移补偿的参考电平生成的方法。 在一个实施例中，产生任意参考电平以提供补偿读出放大器的器件失配和电压阈值的偏移。

公开(公告)号：US20100032742A1

公开(公告)日：2010-02-11

申请号：US12186780

申请日：2008-08-06

申请人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated circuit.

摘要翻译： 一种形成集成电路的方法包括：提供半导体形貌，其包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着外围设置 用于隔离沟槽电容器的沟槽电容器; 在半导体形貌上形成层间电介质; 同时蚀刻（i）通过层间电介质到有源晶体管和沟槽电容器的漏极结的第一开口，以及（ii）通过层间电介质到有源晶体管的源极结的第二开口; 以及用导电材料填充第一开口和第二开口以形成用于将沟槽电容器电连接到有源晶体管的漏极结的带，并且还形成用于将源极结连接到集成的上覆层 电路。

公开(公告)号：US20090158224A1

公开(公告)日：2009-06-18

申请号：US12128197

申请日：2008-05-28

申请人： John E. Barth, JR. ,  Stephen F. Sliva

发明人： John E. Barth, JR. ,  Stephen F. Sliva

IPC分类号： G06F17/50

CPC分类号： G11C29/24 ,  G11C29/72 ,  G11C2029/4402

摘要： Disclosed is design structure including an integrated circuit having a system for moving a failing address into a new FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. Disclosed is an any-for-any scheme that eliminates the tri-state address bus. The design structure allows for easy, discrete scaling with the addition of more FARs, while also allowing larger addresses with no additional control circuit overhead.

摘要翻译： 公开了包括集成电路的集成电路，该集成电路具有通过在冗余存储器元件的BIST期间利用功能比较电路将故障地址移动到新的FAR中的系统。 公开了一种消除三态地址总线的任何方案。 该设计结构允许通过添加更多FAR来实现简单，离散的缩放，同时还允许更大的地址，而无需额外的控制电路开销。

公开(公告)号：US20090144507A1

公开(公告)日：2009-06-04

申请号：US11950015

申请日：2007-12-04

申请人： John E. Barth, JR. ,  Erik L. Hedberg ,  Robert M. Houle ,  Hillery C. Hunter ,  Peter A. Sandon

发明人： John E. Barth, JR. ,  Erik L. Hedberg ,  Robert M. Houle ,  Hillery C. Hunter ,  Peter A. Sandon

IPC分类号： G06F12/08

CPC分类号： G06F12/0893 ,  G06F12/0891 ,  Y02D10/13

摘要： An apparatus for implementing a refreshless, embedded dynamic random access memory (eDRAM) cache device includes a cache structure having a cache tag array associated with a DRAM data cache with a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, the defined assessment period being smaller than retention time of data in the DRAM data cache. For any of the cache lines that have not been accessed during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.

摘要翻译： 一种用于实现无刷嵌入式动态随机存取存储器（eDRAM）高速缓存设备的装置包括具有与具有多个高速缓存线的DRAM数据高速缓存相关联的高速缓存标签阵列的高速缓存结构，高速缓存标签阵列具有地址标签，有效的 位和对应于所述多个高速缓存行中的每一条的存取位; 并且每个访问位被配置为指示在定义的评估周期期间作为读取或写入操作的结果是否已经访问了相应的高速缓存行，所述定义的评估周期小于DRAM数据高速缓存中的数据的保留时间。 对于在定义的评估周期期间未被访问的任何高速缓存行，将与其相关联的单个有效位设置为指示相关联的高速缓存行中的数据无效的逻辑状态。

公开(公告)号：US20090144504A1

公开(公告)日：2009-06-04

申请号：US12116234

申请日：2008-05-07

申请人： John E. Barth, JR. ,  Erik L. Hedberg ,  Robert M. Houle ,  Hillery C. Hunter ,  Peter A. Sandon

发明人： John E. Barth, JR. ,  Erik L. Hedberg ,  Robert M. Houle ,  Hillery C. Hunter ,  Peter A. Sandon

IPC分类号： G06F12/00

CPC分类号： G06F12/0893

摘要： A design structure embodied in a machine readable medium used in a design process includes a cache structure having a cache tag array associated with a eDRAM data cache comprising a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, which is smaller than retention time of data in the DRAM data cache; wherein, for any of the cache lines not accessed as a result of a read or a write operation during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括具有与包括多个高速缓存线的eDRAM数据高速缓存相关联的高速缓存标签阵列的高速缓存结构，高速缓存标签阵列具有地址标签，有效位和 对应于所述多个高速缓存行中的每一个的存取位; 并且每个访问位被配置为指示在定义的评估周期期间作为读取或写入操作的结果是否已经访问了相应的高速缓存行，其小于DRAM数据高速缓存中的数据的保留时间; 其中，对于在定义的评估周期期间作为读取或写入操作的结果未被访问的任何高速缓存行，将与其相关联的各个有效位设置为指示相关联的高速缓存行中的数据无效的逻辑状态。